MIPS: Netlogic: Merge some of XLR/XLP wakup code

Create a common NMI and reset handler in smpboot.S and use this for
both XLR and XLP.  In the earlier code, the woken up CPUs would
busy wait until released, switch this to wakeup by NMI.

The initial wakeup code or XLR and XLP are differ since they are
started from different bootloaders (XLP from u-boot and XLR from
netlogic bootloader). But in both platforms the woken up CPUs wait
and are released by sending an NMI.

Add support for starting XLR and XLP in 1/2/4 threads per core.

Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2970/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

4 files changed, 14 insertions, 112 deletions

diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile
index df245c604547..f01e4d7a0600 100644
--- a/arch/mips/netlogic/xlr/Makefile
+++ b/arch/mips/netlogic/xlr/Makefile
@@ -1,2 +1,2 @@
 obj-y                           += setup.o platform.o
-obj-$(CONFIG_SMP)               += smpboot.o wakeup.o
+obj-$(CONFIG_SMP)               += wakeup.o
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index 20c280ae7e99..c9d066dedc4e 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -52,9 +52,14 @@
 
 uint64_t nlm_io_base = DEFAULT_NETLOGIC_IO_BASE;
 uint64_t nlm_pic_base;
-unsigned long nlm_common_ebase = 0x0;
 struct psb_info nlm_prom_info;
 
+unsigned long nlm_common_ebase = 0x0;
+
+/* default to uniprocessor */
+uint32_t nlm_coremask = 1, nlm_cpumask  = 1;
+int  nlm_threads_per_core = 1;
+
 static void __init nlm_early_serial_setup(void)
 {
         struct uart_port s;
diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/smpboot.S
deleted file mode 100644
index 7f1f6e6e295f..000000000000
--- a/arch/mips/netlogic/xlr/smpboot.S
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <linux/init.h>
-
-#include <asm/asm.h>
-#include <asm/asm-offsets.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-
-/*
- * Early code for secondary CPUs. This will get them out of the bootloader
- * code and into linux. Needed because the bootloader area will be taken
- * and initialized by linux.
- */
-        __CPUINIT
-NESTED(prom_pre_boot_secondary_cpus, 16, sp)
-        .set    mips64
-        mfc0    t0, $15, 1      # read ebase
-        andi    t0, 0x1f        # t0 has the processor_id()
-        sll     t0, 2           # offset in cpu array
-
-        PTR_LA  t1, nlm_cpu_ready # mark CPU ready
-        PTR_ADDU t1, t0
-        li      t2, 1
-        sw      t2, 0(t1)
-
-        PTR_LA  t1, nlm_cpu_unblock
-        PTR_ADDU t1, t0
-1:      lw      t2, 0(t1)       # wait till unblocked
-        beqz    t2, 1b
-        nop
-
-        PTR_LA  t1, nlm_next_sp
-        PTR_L   sp, 0(t1)
-        PTR_LA  t1, nlm_next_gp
-        PTR_L   gp, 0(t1)
-
-        PTR_LA  t0, nlm_early_init_secondary
-        jalr    t0
-        nop
-
-        PTR_LA  t0, smp_bootstrap
-        jr      t0
-        nop
-END(prom_pre_boot_secondary_cpus)
-
-/*
- * NMI code, used for CPU wakeup, copied to reset entry
- */
-EXPORT(nlm_reset_entry)
-        .set push
-        .set noat
-        .set mips64
-        .set noreorder
-
-        /* Clear the  NMI and BEV bits */
-        MFC0    k0, CP0_STATUS
-        li      k1, 0xffb7ffff
-        and     k0, k0, k1
-        MTC0    k0, CP0_STATUS
-
-        PTR_LA  k1, secondary_entry_point
-        PTR_L   k0, 0(k1)
-        jr      k0
-        nop
-        .set pop
-EXPORT(nlm_reset_entry_end)
-        __FINIT
diff --git a/arch/mips/netlogic/xlr/wakeup.c b/arch/mips/netlogic/xlr/wakeup.c
index 69143bb7f688..db5d987d4881 100644
--- a/arch/mips/netlogic/xlr/wakeup.c
+++ b/arch/mips/netlogic/xlr/wakeup.c
@@ -48,21 +48,18 @@
 #include <asm/netlogic/xlr/iomap.h>
 #include <asm/netlogic/xlr/pic.h>
 
-unsigned long secondary_entry_point;
-
-int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
+int __cpuinit xlr_wakeup_secondary_cpus(void)
 {
         unsigned int i, boot_cpu;
-        void *reset_vec;
 
-        secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus;
-        reset_vec = (void *)CKSEG1ADDR(0x1fc00000);
-        memcpy(reset_vec, (void *)nlm_reset_entry,
-                        (nlm_reset_entry_end - nlm_reset_entry));
+        /*
+         *  In case of RMI boot, hit with NMI to get the cores
+         *  from bootloader to linux code.
+         */
         boot_cpu = hard_smp_processor_id();
-
+        nlm_set_nmi_handler(nlm_rmiboot_preboot);
         for (i = 0; i < NR_CPUS; i++) {
-                if (i == boot_cpu || (wakeup_mask & (1u << i)) == 0)
+                if (i == boot_cpu || (nlm_cpumask & (1u << i)) == 0)
                         continue;
                 nlm_pic_send_ipi(nlm_pic_base, i, 1, 1); /* send NMI */
         }