MIPS: Netlogic: Merge some of XLR/XLP wakup code

Create a common NMI and reset handler in smpboot.S and use this for
both XLR and XLP.  In the earlier code, the woken up CPUs would
busy wait until released, switch this to wakeup by NMI.

The initial wakeup code or XLR and XLP are differ since they are
started from different bootloaders (XLP from u-boot and XLR from
netlogic bootloader). But in both platforms the woken up CPUs wait
and are released by sending an NMI.

Add support for starting XLR and XLP in 1/2/4 threads per core.

Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2970/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 7 insertions, 10 deletions

diff --git a/arch/mips/netlogic/xlr/wakeup.c b/arch/mips/netlogic/xlr/wakeup.c
index 69143bb7f688..db5d987d4881 100644
--- a/arch/mips/netlogic/xlr/wakeup.c
+++ b/arch/mips/netlogic/xlr/wakeup.c
@@ -48,21 +48,18 @@
 #include <asm/netlogic/xlr/iomap.h>
 #include <asm/netlogic/xlr/pic.h>
 
-unsigned long secondary_entry_point;
-
-int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
+int __cpuinit xlr_wakeup_secondary_cpus(void)
 {
         unsigned int i, boot_cpu;
-        void *reset_vec;
 
-        secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus;
-        reset_vec = (void *)CKSEG1ADDR(0x1fc00000);
-        memcpy(reset_vec, (void *)nlm_reset_entry,
-                        (nlm_reset_entry_end - nlm_reset_entry));
+        /*
+         *  In case of RMI boot, hit with NMI to get the cores
+         *  from bootloader to linux code.
+         */
         boot_cpu = hard_smp_processor_id();
-
+        nlm_set_nmi_handler(nlm_rmiboot_preboot);
         for (i = 0; i < NR_CPUS; i++) {
-                if (i == boot_cpu || (wakeup_mask & (1u << i)) == 0)
+                if (i == boot_cpu || (nlm_cpumask & (1u << i)) == 0)
                         continue;
                 nlm_pic_send_ipi(nlm_pic_base, i, 1, 1); /* send NMI */
         }