MIPS: Netlogic: PIC freq calculation for XLP 9XX/2XX

Update PIC frequency calculation for XLP9XX and 2XX processors using
the correct PLL registers. This should work for all possible board
configurations.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6876/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 81 insertions, 33 deletions

diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 9f9814d646a9..59f1303b69d7 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -234,21 +234,28 @@ unsigned int nlm_get_core_frequency(int node, int core)
         return (unsigned int)num;
 }
 
-/* Calculate Frequency to the PIC from PLL.
- * freq_out = ( ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13 ) /
- * ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
+/*
+ * Calculate PIC frequency from PLL registers.
+ * freq_out = (ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13) /
+ *              ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
  */
-static unsigned int nlm_2xx_get_pic_frequency(int node)
+static unsigned int nlm_xlp2_get_pic_frequency(int node)
 {
-        u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div;
+        u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div, cpu_xlp9xx;
         u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
-        u64 ref_clk, sysbase, pll_out_freq_num, ref_clk_select;
+        u64 sysbase, pll_out_freq_num, ref_clk_select, clockbase, ref_clk;
 
         sysbase = nlm_get_node(node)->sysbase;
+        clockbase = nlm_get_clock_regbase(node);
+        cpu_xlp9xx = cpu_is_xlp9xx();
 
         /* Find ref_clk_base */
-        ref_clk_select =
-                (nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
+        if (cpu_xlp9xx)
+                ref_clk_select = (nlm_read_sys_reg(sysbase,
+                                SYS_9XX_POWER_ON_RESET_CFG) >> 18) & 0x3;
+        else
+                ref_clk_select = (nlm_read_sys_reg(sysbase,
+                                        SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
         switch (ref_clk_select) {
         case 0:
                 ref_clk = 200000000ULL;
@@ -269,30 +276,70 @@ static unsigned int nlm_2xx_get_pic_frequency(int node)
         }
 
         /* Find the clock source PLL device for PIC */
-        reg_select = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_SEL) >> 22) & 0x3;
-        switch (reg_select) {
-        case 0:
-                ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0);
-                ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2);
-                break;
-        case 1:
-                ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(0));
-                ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(0));
-                break;
-        case 2:
-                ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(1));
-                ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(1));
-                break;
-        case 3:
-                ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(2));
-                ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(2));
-                break;
+        if (cpu_xlp9xx) {
+                reg_select = nlm_read_sys_reg(clockbase,
+                                SYS_9XX_CLK_DEV_SEL) & 0x3;
+                switch (reg_select) {
+                case 0:
+                        ctrl_val0 = nlm_read_sys_reg(clockbase,
+                                        SYS_9XX_PLL_CTRL0);
+                        ctrl_val2 = nlm_read_sys_reg(clockbase,
+                                        SYS_9XX_PLL_CTRL2);
+                        break;
+                case 1:
+                        ctrl_val0 = nlm_read_sys_reg(clockbase,
+                                        SYS_9XX_PLL_CTRL0_DEVX(0));
+                        ctrl_val2 = nlm_read_sys_reg(clockbase,
+                                        SYS_9XX_PLL_CTRL2_DEVX(0));
+                        break;
+                case 2:
+                        ctrl_val0 = nlm_read_sys_reg(clockbase,
+                                        SYS_9XX_PLL_CTRL0_DEVX(1));
+                        ctrl_val2 = nlm_read_sys_reg(clockbase,
+                                        SYS_9XX_PLL_CTRL2_DEVX(1));
+                        break;
+                case 3:
+                        ctrl_val0 = nlm_read_sys_reg(clockbase,
+                                        SYS_9XX_PLL_CTRL0_DEVX(2));
+                        ctrl_val2 = nlm_read_sys_reg(clockbase,
+                                        SYS_9XX_PLL_CTRL2_DEVX(2));
+                        break;
+                }
+        } else {
+                reg_select = (nlm_read_sys_reg(sysbase,
+                                        SYS_CLK_DEV_SEL) >> 22) & 0x3;
+                switch (reg_select) {
+                case 0:
+                        ctrl_val0 = nlm_read_sys_reg(sysbase,
+                                        SYS_PLL_CTRL0);
+                        ctrl_val2 = nlm_read_sys_reg(sysbase,
+                                        SYS_PLL_CTRL2);
+                        break;
+                case 1:
+                        ctrl_val0 = nlm_read_sys_reg(sysbase,
+                                        SYS_PLL_CTRL0_DEVX(0));
+                        ctrl_val2 = nlm_read_sys_reg(sysbase,
+                                        SYS_PLL_CTRL2_DEVX(0));
+                        break;
+                case 2:
+                        ctrl_val0 = nlm_read_sys_reg(sysbase,
+                                        SYS_PLL_CTRL0_DEVX(1));
+                        ctrl_val2 = nlm_read_sys_reg(sysbase,
+                                        SYS_PLL_CTRL2_DEVX(1));
+                        break;
+                case 3:
+                        ctrl_val0 = nlm_read_sys_reg(sysbase,
+                                        SYS_PLL_CTRL0_DEVX(2));
+                        ctrl_val2 = nlm_read_sys_reg(sysbase,
+                                        SYS_PLL_CTRL2_DEVX(2));
+                        break;
+                }
         }
 
         vco_post_div = (ctrl_val0 >> 5) & 0x7;
         pll_post_div = (ctrl_val0 >> 24) & 0x7;
         mdiv = ctrl_val2 & 0xff;
-        fdiv = (ctrl_val2 >> 8) & 0xfff;
+        fdiv = (ctrl_val2 >> 8) & 0x1fff;
 
         /* Find PLL post divider value */
         switch (pll_post_div) {
@@ -322,7 +369,12 @@ static unsigned int nlm_2xx_get_pic_frequency(int node)
                 do_div(pll_out_freq_num, pll_out_freq_den);
 
         /* PIC post divider, which happens after PLL */
-        pic_div = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_DIV) >> 22) & 0x3;
+        if (cpu_xlp9xx)
+                pic_div = nlm_read_sys_reg(clockbase,
+                                SYS_9XX_CLK_DEV_DIV) & 0x3;
+        else
+                pic_div = (nlm_read_sys_reg(sysbase,
+                                        SYS_CLK_DEV_DIV) >> 22) & 0x3;
         do_div(pll_out_freq_num, 1 << pic_div);
 
         return pll_out_freq_num;
@@ -330,12 +382,8 @@ static unsigned int nlm_2xx_get_pic_frequency(int node)
 
 unsigned int nlm_get_pic_frequency(int node)
 {
-        /* TODO Has to calculate freq as like 2xx */
-        if (cpu_is_xlp9xx())
-                return 250000000;
-
         if (cpu_is_xlpii())
-                return nlm_2xx_get_pic_frequency(node);
+                return nlm_xlp2_get_pic_frequency(node);
         else
                 return 133333333;
 }