diff options
author | Jayachandran C <jchandra@broadcom.com> | 2013-06-10 02:41:04 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2013-06-13 11:46:42 -0400 |
commit | 919f9abb3723f088290c62648b12fbfc7600d923 (patch) | |
tree | 00d1373418b59a086874a31a9cb5fefb16985cb9 /arch/mips/netlogic/common | |
parent | 53c832197f3adc5a360336f75fe34a95fe2d796b (diff) |
MIPS: Netlogic: move cpu_ready array to boot area
Move the nlm_cpu_ready[] array used by the cpu wakeup code to the
boot area, along with rest of the boot parameter code.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5425/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/netlogic/common')
-rw-r--r-- | arch/mips/netlogic/common/reset.S | 6 | ||||
-rw-r--r-- | arch/mips/netlogic/common/smp.c | 6 | ||||
-rw-r--r-- | arch/mips/netlogic/common/smpboot.S | 5 |
3 files changed, 10 insertions, 7 deletions
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S index 98691d6b3bbe..b11691c629d0 100644 --- a/arch/mips/netlogic/common/reset.S +++ b/arch/mips/netlogic/common/reset.S | |||
@@ -216,8 +216,10 @@ EXPORT(nlm_boot_siblings) | |||
216 | ori t1, ST0_KX | 216 | ori t1, ST0_KX |
217 | #endif | 217 | #endif |
218 | mtc0 t1, CP0_STATUS | 218 | mtc0 t1, CP0_STATUS |
219 | /* mark CPU ready */ | 219 | |
220 | PTR_LA t1, nlm_cpu_ready | 220 | /* mark CPU ready, careful here, previous mtcr trashed registers */ |
221 | li t3, CKSEG1ADDR(RESET_DATA_PHYS) | ||
222 | ADDIU t1, t3, BOOT_CPU_READY | ||
221 | sll v1, v0, 2 | 223 | sll v1, v0, 2 |
222 | PTR_ADDU t1, v1 | 224 | PTR_ADDU t1, v1 |
223 | li t2, 1 | 225 | li t2, 1 |
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c index 1f66eef3aea7..885d293b61da 100644 --- a/arch/mips/netlogic/common/smp.c +++ b/arch/mips/netlogic/common/smp.c | |||
@@ -145,7 +145,6 @@ void nlm_cpus_done(void) | |||
145 | * Boot all other cpus in the system, initialize them, and bring them into | 145 | * Boot all other cpus in the system, initialize them, and bring them into |
146 | * the boot function | 146 | * the boot function |
147 | */ | 147 | */ |
148 | int nlm_cpu_ready[NR_CPUS]; | ||
149 | unsigned long nlm_next_gp; | 148 | unsigned long nlm_next_gp; |
150 | unsigned long nlm_next_sp; | 149 | unsigned long nlm_next_sp; |
151 | static cpumask_t phys_cpu_present_mask; | 150 | static cpumask_t phys_cpu_present_mask; |
@@ -168,6 +167,7 @@ void __init nlm_smp_setup(void) | |||
168 | { | 167 | { |
169 | unsigned int boot_cpu; | 168 | unsigned int boot_cpu; |
170 | int num_cpus, i, ncore; | 169 | int num_cpus, i, ncore; |
170 | volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); | ||
171 | char buf[64]; | 171 | char buf[64]; |
172 | 172 | ||
173 | boot_cpu = hard_smp_processor_id(); | 173 | boot_cpu = hard_smp_processor_id(); |
@@ -181,10 +181,10 @@ void __init nlm_smp_setup(void) | |||
181 | num_cpus = 1; | 181 | num_cpus = 1; |
182 | for (i = 0; i < NR_CPUS; i++) { | 182 | for (i = 0; i < NR_CPUS; i++) { |
183 | /* | 183 | /* |
184 | * nlm_cpu_ready array is not set for the boot_cpu, | 184 | * cpu_ready array is not set for the boot_cpu, |
185 | * it is only set for ASPs (see smpboot.S) | 185 | * it is only set for ASPs (see smpboot.S) |
186 | */ | 186 | */ |
187 | if (nlm_cpu_ready[i]) { | 187 | if (cpu_ready[i]) { |
188 | cpumask_set_cpu(i, &phys_cpu_present_mask); | 188 | cpumask_set_cpu(i, &phys_cpu_present_mask); |
189 | __cpu_number_map[i] = num_cpus; | 189 | __cpu_number_map[i] = num_cpus; |
190 | __cpu_logical_map[num_cpus] = i; | 190 | __cpu_logical_map[num_cpus] = i; |
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S index 7c7e884f8912..6029d1b37f88 100644 --- a/arch/mips/netlogic/common/smpboot.S +++ b/arch/mips/netlogic/common/smpboot.S | |||
@@ -109,8 +109,9 @@ NESTED(nlm_rmiboot_preboot, 16, sp) | |||
109 | andi t2, t0, 0x3 /* thread num */ | 109 | andi t2, t0, 0x3 /* thread num */ |
110 | sll t0, 2 /* offset in cpu array */ | 110 | sll t0, 2 /* offset in cpu array */ |
111 | 111 | ||
112 | PTR_LA t1, nlm_cpu_ready /* mark CPU ready */ | 112 | li t3, CKSEG1ADDR(RESET_DATA_PHYS) |
113 | PTR_ADDU t1, t0 | 113 | ADDIU t1, t3, BOOT_CPU_READY |
114 | ADDU t1, t0 | ||
114 | li t3, 1 | 115 | li t3, 1 |
115 | sw t3, 0(t1) | 116 | sw t3, 0(t1) |
116 | 117 | ||