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authorRalf Baechle <ralf@linux-mips.org>2013-01-22 06:59:30 -0500
committerRalf Baechle <ralf@linux-mips.org>2013-02-01 04:00:22 -0500
commit7034228792cc561e79ff8600f02884bd4c80e287 (patch)
tree89b77af37d087d9de236fc5d21f60bf552d0a2c6 /arch/mips/netlogic/common/smpboot.S
parent405ab01c70e18058d9c01a1256769a61fc65413e (diff)
MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/netlogic/common/smpboot.S')
-rw-r--r--arch/mips/netlogic/common/smpboot.S14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index a0b74874bebe..280ff5855ef7 100644
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -49,12 +49,12 @@
49#include <asm/netlogic/xlp-hal/sys.h> 49#include <asm/netlogic/xlp-hal/sys.h>
50#include <asm/netlogic/xlp-hal/cpucontrol.h> 50#include <asm/netlogic/xlp-hal/cpucontrol.h>
51 51
52#define CP0_EBASE $15 52#define CP0_EBASE $15
53#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \ 53#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ 54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
55 SYS_CPU_NONCOHERENT_MODE * 4 55 SYS_CPU_NONCOHERENT_MODE * 4
56 56
57#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */ 57#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */
58 58
59/* Enable XLP features and workarounds in the LSU */ 59/* Enable XLP features and workarounds in the LSU */
60.macro xlp_config_lsu 60.macro xlp_config_lsu
@@ -85,7 +85,7 @@
85 li t0, LSU_DEBUG_DATA0 85 li t0, LSU_DEBUG_DATA0
86 li t1, LSU_DEBUG_ADDR 86 li t1, LSU_DEBUG_ADDR
87 li t2, 0 /* index */ 87 li t2, 0 /* index */
88 li t3, 0x1000 /* loop count */ 88 li t3, 0x1000 /* loop count */
891: 891:
90 sll v0, t2, 5 90 sll v0, t2, 5
91 mtcr zero, t0 91 mtcr zero, t0
@@ -134,7 +134,7 @@ FEXPORT(nlm_reset_entry)
134 and k1, k0, k1 134 and k1, k0, k1
135 beqz k1, 1f /* go to real reset entry */ 135 beqz k1, 1f /* go to real reset entry */
136 nop 136 nop
137 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ 137 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
138 ld k0, BOOT_NMI_HANDLER(k1) 138 ld k0, BOOT_NMI_HANDLER(k1)
139 jr k0 139 jr k0
140 nop 140 nop
@@ -235,7 +235,7 @@ EXPORT(nlm_reset_entry_end)
235 235
236FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */ 236FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
237 xlp_config_lsu 237 xlp_config_lsu
238 dmtc0 sp, $4, 2 /* SP saved in UserLocal */ 238 dmtc0 sp, $4, 2 /* SP saved in UserLocal */
239 SAVE_ALL 239 SAVE_ALL
240 sync 240 sync
241 /* find the location to which nlm_boot_siblings was relocated */ 241 /* find the location to which nlm_boot_siblings was relocated */
@@ -301,13 +301,13 @@ NESTED(nlm_rmiboot_preboot, 16, sp)
301 */ 301 */
302 li t0, 0x400 302 li t0, 0x400
303 mfcr t1, t0 303 mfcr t1, t0
304 li t2, 6 /* XLR thread mode mask */ 304 li t2, 6 /* XLR thread mode mask */
305 nor t3, t2, zero 305 nor t3, t2, zero
306 and t2, t1, t2 /* t2 - current thread mode */ 306 and t2, t1, t2 /* t2 - current thread mode */
307 li v0, CKSEG1ADDR(RESET_DATA_PHYS) 307 li v0, CKSEG1ADDR(RESET_DATA_PHYS)
308 lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */ 308 lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
309 sll v1, 1 309 sll v1, 1
310 beq v1, t2, 1f /* same as request value */ 310 beq v1, t2, 1f /* same as request value */
311 nop /* nothing to do */ 311 nop /* nothing to do */
312 312
313 and t2, t1, t3 /* mask out old thread mode */ 313 and t2, t1, t3 /* mask out old thread mode */