diff options
author | Jayachandran C <jchandra@broadcom.com> | 2012-10-31 08:01:37 -0400 |
---|---|---|
committer | John Crispin <blogic@openwrt.org> | 2012-11-09 05:37:19 -0500 |
commit | 2a37b1ae443f20470a789b12a45cbc249c9e50a6 (patch) | |
tree | 101eacbdbc8a34ae7bcd0da8950972165f00d253 /arch/mips/netlogic/common/smp.c | |
parent | 7143246e9ace7f6b50aad217289dd64b7a44dd2c (diff) |
MIPS: Netlogic: Move from u32 cpumask to cpumask_t
Initial code to support more than 32 cpus. The platform CPU mask
is updated from 32-bit mask to cpumask_t. Convert places that use
cpu_/cpus_ functions to use cpumask_* functions.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4464
Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch/mips/netlogic/common/smp.c')
-rw-r--r-- | arch/mips/netlogic/common/smp.c | 39 |
1 files changed, 20 insertions, 19 deletions
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c index cd39f5429e8a..4fe8992b291c 100644 --- a/arch/mips/netlogic/common/smp.c +++ b/arch/mips/netlogic/common/smp.c | |||
@@ -160,9 +160,9 @@ void __init nlm_smp_setup(void) | |||
160 | int num_cpus, i; | 160 | int num_cpus, i; |
161 | 161 | ||
162 | boot_cpu = hard_smp_processor_id(); | 162 | boot_cpu = hard_smp_processor_id(); |
163 | cpus_clear(phys_cpu_present_map); | 163 | cpumask_clear(&phys_cpu_present_map); |
164 | 164 | ||
165 | cpu_set(boot_cpu, phys_cpu_present_map); | 165 | cpumask_set_cpu(boot_cpu, &phys_cpu_present_map); |
166 | __cpu_number_map[boot_cpu] = 0; | 166 | __cpu_number_map[boot_cpu] = 0; |
167 | __cpu_logical_map[0] = boot_cpu; | 167 | __cpu_logical_map[0] = boot_cpu; |
168 | set_cpu_possible(0, true); | 168 | set_cpu_possible(0, true); |
@@ -174,7 +174,7 @@ void __init nlm_smp_setup(void) | |||
174 | * it is only set for ASPs (see smpboot.S) | 174 | * it is only set for ASPs (see smpboot.S) |
175 | */ | 175 | */ |
176 | if (nlm_cpu_ready[i]) { | 176 | if (nlm_cpu_ready[i]) { |
177 | cpu_set(i, phys_cpu_present_map); | 177 | cpumask_set_cpu(i, &phys_cpu_present_map); |
178 | __cpu_number_map[i] = num_cpus; | 178 | __cpu_number_map[i] = num_cpus; |
179 | __cpu_logical_map[num_cpus] = i; | 179 | __cpu_logical_map[num_cpus] = i; |
180 | set_cpu_possible(num_cpus, true); | 180 | set_cpu_possible(num_cpus, true); |
@@ -183,19 +183,22 @@ void __init nlm_smp_setup(void) | |||
183 | } | 183 | } |
184 | 184 | ||
185 | pr_info("Phys CPU present map: %lx, possible map %lx\n", | 185 | pr_info("Phys CPU present map: %lx, possible map %lx\n", |
186 | (unsigned long)phys_cpu_present_map.bits[0], | 186 | (unsigned long)cpumask_bits(&phys_cpu_present_map)[0], |
187 | (unsigned long)cpumask_bits(cpu_possible_mask)[0]); | 187 | (unsigned long)cpumask_bits(cpu_possible_mask)[0]); |
188 | 188 | ||
189 | pr_info("Detected %i Slave CPU(s)\n", num_cpus); | 189 | pr_info("Detected %i Slave CPU(s)\n", num_cpus); |
190 | nlm_set_nmi_handler(nlm_boot_secondary_cpus); | 190 | nlm_set_nmi_handler(nlm_boot_secondary_cpus); |
191 | } | 191 | } |
192 | 192 | ||
193 | static int nlm_parse_cpumask(u32 cpu_mask) | 193 | static int nlm_parse_cpumask(cpumask_t *wakeup_mask) |
194 | { | 194 | { |
195 | uint32_t core0_thr_mask, core_thr_mask; | 195 | uint32_t core0_thr_mask, core_thr_mask; |
196 | int threadmode, i; | 196 | int threadmode, i, j; |
197 | 197 | ||
198 | core0_thr_mask = cpu_mask & 0xf; | 198 | core0_thr_mask = 0; |
199 | for (i = 0; i < 4; i++) | ||
200 | if (cpumask_test_cpu(i, wakeup_mask)) | ||
201 | core0_thr_mask |= (1 << i); | ||
199 | switch (core0_thr_mask) { | 202 | switch (core0_thr_mask) { |
200 | case 1: | 203 | case 1: |
201 | nlm_threads_per_core = 1; | 204 | nlm_threads_per_core = 1; |
@@ -214,25 +217,23 @@ static int nlm_parse_cpumask(u32 cpu_mask) | |||
214 | } | 217 | } |
215 | 218 | ||
216 | /* Verify other cores CPU masks */ | 219 | /* Verify other cores CPU masks */ |
217 | nlm_coremask = 1; | 220 | for (i = 0; i < NR_CPUS; i += 4) { |
218 | nlm_cpumask = core0_thr_mask; | 221 | core_thr_mask = 0; |
219 | for (i = 1; i < 8; i++) { | 222 | for (j = 0; j < 4; j++) |
220 | core_thr_mask = (cpu_mask >> (i * 4)) & 0xf; | 223 | if (cpumask_test_cpu(i + j, wakeup_mask)) |
221 | if (core_thr_mask) { | 224 | core_thr_mask |= (1 << j); |
222 | if (core_thr_mask != core0_thr_mask) | 225 | if (core_thr_mask != 0 && core_thr_mask != core0_thr_mask) |
223 | goto unsupp; | 226 | goto unsupp; |
224 | nlm_coremask |= 1 << i; | ||
225 | nlm_cpumask |= core0_thr_mask << (4 * i); | ||
226 | } | ||
227 | } | 227 | } |
228 | return threadmode; | 228 | return threadmode; |
229 | 229 | ||
230 | unsupp: | 230 | unsupp: |
231 | panic("Unsupported CPU mask %x\n", cpu_mask); | 231 | panic("Unsupported CPU mask %lx\n", |
232 | (unsigned long)cpumask_bits(wakeup_mask)[0]); | ||
232 | return 0; | 233 | return 0; |
233 | } | 234 | } |
234 | 235 | ||
235 | int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask) | 236 | int __cpuinit nlm_wakeup_secondary_cpus(void) |
236 | { | 237 | { |
237 | unsigned long reset_vec; | 238 | unsigned long reset_vec; |
238 | char *reset_data; | 239 | char *reset_data; |
@@ -244,7 +245,7 @@ int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask) | |||
244 | (nlm_reset_entry_end - nlm_reset_entry)); | 245 | (nlm_reset_entry_end - nlm_reset_entry)); |
245 | 246 | ||
246 | /* verify the mask and setup core config variables */ | 247 | /* verify the mask and setup core config variables */ |
247 | threadmode = nlm_parse_cpumask(wakeup_mask); | 248 | threadmode = nlm_parse_cpumask(&nlm_cpumask); |
248 | 249 | ||
249 | /* Setup CPU init parameters */ | 250 | /* Setup CPU init parameters */ |
250 | reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS); | 251 | reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS); |