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authorChris Dearman <chris@mips.com>2009-07-10 04:53:54 -0400
committerRalf Baechle <ralf@linux-mips.org>2009-11-02 06:00:04 -0500
commitaccfd35a4e82148ff3d6e1946c1786e73fb408fd (patch)
tree213b840ce84cdd635c9f0344dea693fe9313371b /arch/mips/mti-malta
parent0f334a3e8c3586f81286345eb077ed32b375e8d6 (diff)
MIPS: MTI: Fix accesses to device registers on MIPS boards
This fixes the remaining problems introduced by f197465384bf7ef1af184c2ed1a4e268911a91e3 (incorrect access length & byteswapping in bigendian mode) Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mti-malta')
-rw-r--r--arch/mips/mti-malta/malta-int.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 3e0a9b35ba5c..e568d0da060e 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -87,7 +87,7 @@ static inline int mips_pcibios_iack(void)
87 dummy = BONITO_PCIMAP_CFG; 87 dummy = BONITO_PCIMAP_CFG;
88 iob(); /* sync */ 88 iob(); /* sync */
89 89
90 irq = readl((u32 *)_pcictrl_bonito_pcicfg); 90 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
91 iob(); /* sync */ 91 iob(); /* sync */
92 irq &= 0xff; 92 irq &= 0xff;
93 BONITO_PCIMAP_CFG = 0; 93 BONITO_PCIMAP_CFG = 0;