diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2013-02-21 06:51:33 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2013-02-21 06:51:33 -0500 |
commit | 8bfc245f9ad7bd4e461179e4e7852ef99b8b6144 (patch) | |
tree | 0ad091f645fbc8318634599d278966a53d3922ee /arch/mips/mti-malta | |
parent | 612663a974065c3445e641d046769fe4c55a6438 (diff) | |
parent | 535237cecab2b078114be712c67e89a0db61965f (diff) |
Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
Diffstat (limited to 'arch/mips/mti-malta')
-rw-r--r-- | arch/mips/mti-malta/malta-time.c | 83 |
1 files changed, 50 insertions, 33 deletions
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index 8607b0dd29f6..a144b89cf9ba 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c | |||
@@ -17,7 +17,6 @@ | |||
17 | * | 17 | * |
18 | * Setting up the clock on the MIPS boards. | 18 | * Setting up the clock on the MIPS boards. |
19 | */ | 19 | */ |
20 | |||
21 | #include <linux/types.h> | 20 | #include <linux/types.h> |
22 | #include <linux/i8253.h> | 21 | #include <linux/i8253.h> |
23 | #include <linux/init.h> | 22 | #include <linux/init.h> |
@@ -25,7 +24,6 @@ | |||
25 | #include <linux/sched.h> | 24 | #include <linux/sched.h> |
26 | #include <linux/spinlock.h> | 25 | #include <linux/spinlock.h> |
27 | #include <linux/interrupt.h> | 26 | #include <linux/interrupt.h> |
28 | #include <linux/time.h> | ||
29 | #include <linux/timex.h> | 27 | #include <linux/timex.h> |
30 | #include <linux/mc146818rtc.h> | 28 | #include <linux/mc146818rtc.h> |
31 | 29 | ||
@@ -34,11 +32,11 @@ | |||
34 | #include <asm/hardirq.h> | 32 | #include <asm/hardirq.h> |
35 | #include <asm/irq.h> | 33 | #include <asm/irq.h> |
36 | #include <asm/div64.h> | 34 | #include <asm/div64.h> |
37 | #include <asm/cpu.h> | ||
38 | #include <asm/setup.h> | 35 | #include <asm/setup.h> |
39 | #include <asm/time.h> | 36 | #include <asm/time.h> |
40 | #include <asm/mc146818-time.h> | 37 | #include <asm/mc146818-time.h> |
41 | #include <asm/msc01_ic.h> | 38 | #include <asm/msc01_ic.h> |
39 | #include <asm/gic.h> | ||
42 | 40 | ||
43 | #include <asm/mips-boards/generic.h> | 41 | #include <asm/mips-boards/generic.h> |
44 | #include <asm/mips-boards/prom.h> | 42 | #include <asm/mips-boards/prom.h> |
@@ -46,6 +44,7 @@ | |||
46 | #include <asm/mips-boards/maltaint.h> | 44 | #include <asm/mips-boards/maltaint.h> |
47 | 45 | ||
48 | unsigned long cpu_khz; | 46 | unsigned long cpu_khz; |
47 | int gic_frequency; | ||
49 | 48 | ||
50 | static int mips_cpu_timer_irq; | 49 | static int mips_cpu_timer_irq; |
51 | static int mips_cpu_perf_irq; | 50 | static int mips_cpu_perf_irq; |
@@ -61,44 +60,50 @@ static void mips_perf_dispatch(void) | |||
61 | do_IRQ(mips_cpu_perf_irq); | 60 | do_IRQ(mips_cpu_perf_irq); |
62 | } | 61 | } |
63 | 62 | ||
63 | static unsigned int freqround(unsigned int freq, unsigned int amount) | ||
64 | { | ||
65 | freq += amount; | ||
66 | freq -= freq % (amount*2); | ||
67 | return freq; | ||
68 | } | ||
69 | |||
64 | /* | 70 | /* |
65 | * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect | 71 | * Estimate CPU and GIC frequencies. |
66 | */ | 72 | */ |
67 | static unsigned int __init estimate_cpu_frequency(void) | 73 | static void __init estimate_frequencies(void) |
68 | { | 74 | { |
69 | unsigned int prid = read_c0_prid() & 0xffff00; | ||
70 | unsigned int count; | ||
71 | |||
72 | unsigned long flags; | 75 | unsigned long flags; |
73 | unsigned int start; | 76 | unsigned int count, start; |
77 | unsigned int giccount = 0, gicstart = 0; | ||
74 | 78 | ||
75 | local_irq_save(flags); | 79 | local_irq_save(flags); |
76 | 80 | ||
77 | /* Start counter exactly on falling edge of update flag */ | 81 | /* Start counter exactly on falling edge of update flag. */ |
78 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); | 82 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
79 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | 83 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); |
80 | 84 | ||
81 | /* Start r4k counter. */ | 85 | /* Initialize counters. */ |
82 | start = read_c0_count(); | 86 | start = read_c0_count(); |
87 | if (gic_present) | ||
88 | GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart); | ||
83 | 89 | ||
84 | /* Read counter exactly on falling edge of update flag */ | 90 | /* Read counter exactly on falling edge of update flag. */ |
85 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); | 91 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
86 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | 92 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); |
87 | 93 | ||
88 | count = read_c0_count() - start; | 94 | count = read_c0_count(); |
95 | if (gic_present) | ||
96 | GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount); | ||
89 | 97 | ||
90 | /* restore interrupts */ | ||
91 | local_irq_restore(flags); | 98 | local_irq_restore(flags); |
92 | 99 | ||
93 | mips_hpt_frequency = count; | 100 | count -= start; |
94 | if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && | 101 | if (gic_present) |
95 | (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) | 102 | giccount -= gicstart; |
96 | count *= 2; | ||
97 | |||
98 | count += 5000; /* round */ | ||
99 | count -= count%10000; | ||
100 | 103 | ||
101 | return count; | 104 | mips_hpt_frequency = count; |
105 | if (gic_present) | ||
106 | gic_frequency = giccount; | ||
102 | } | 107 | } |
103 | 108 | ||
104 | void read_persistent_clock(struct timespec *ts) | 109 | void read_persistent_clock(struct timespec *ts) |
@@ -144,22 +149,34 @@ unsigned int __cpuinit get_c0_compare_int(void) | |||
144 | 149 | ||
145 | void __init plat_time_init(void) | 150 | void __init plat_time_init(void) |
146 | { | 151 | { |
147 | unsigned int est_freq; | 152 | unsigned int prid = read_c0_prid() & 0xffff00; |
148 | 153 | unsigned int freq; | |
149 | /* Set Data mode - binary. */ | ||
150 | CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); | ||
151 | |||
152 | est_freq = estimate_cpu_frequency(); | ||
153 | 154 | ||
154 | printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, | 155 | estimate_frequencies(); |
155 | (est_freq%1000000)*100/1000000); | ||
156 | 156 | ||
157 | cpu_khz = est_freq / 1000; | 157 | freq = mips_hpt_frequency; |
158 | if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && | ||
159 | (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) | ||
160 | freq *= 2; | ||
161 | freq = freqround(freq, 5000); | ||
162 | pr_debug("CPU frequency %d.%02d MHz\n", freq/1000000, | ||
163 | (freq%1000000)*100/1000000); | ||
164 | cpu_khz = freq / 1000; | ||
165 | |||
166 | if (gic_present) { | ||
167 | freq = freqround(gic_frequency, 5000); | ||
168 | pr_debug("GIC frequency %d.%02d MHz\n", freq/1000000, | ||
169 | (freq%1000000)*100/1000000); | ||
170 | gic_clocksource_init(gic_frequency); | ||
171 | } else | ||
172 | init_r4k_clocksource(); | ||
158 | 173 | ||
159 | mips_scroll_message(); | 174 | #ifdef CONFIG_I8253 |
160 | #ifdef CONFIG_I8253 /* Only Malta has a PIT */ | 175 | /* Only Malta has a PIT. */ |
161 | setup_pit_timer(); | 176 | setup_pit_timer(); |
162 | #endif | 177 | #endif |
163 | 178 | ||
179 | mips_scroll_message(); | ||
180 | |||
164 | plat_perf_setup(); | 181 | plat_perf_setup(); |
165 | } | 182 | } |