MIPS: Add option to disable software I/O coherency.

Some MIPS controllers have hardware I/O coherency. This patch
detects those and turns off software coherency. A new kernel
command line option also allows the user to manually turn
software coherency on or off.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>

1 files changed, 63 insertions, 0 deletions

diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index 200f64df2c9b..a85557171faa 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -32,6 +32,7 @@
 #include <asm/mips-boards/maltaint.h>
 #include <asm/dma.h>
 #include <asm/traps.h>
+#include <asm/gcmpregs.h>
 #ifdef CONFIG_VT
 #include <linux/console.h>
 #endif
@@ -105,6 +106,66 @@ static void __init fd_activate(void)
 }
 #endif
 
+static int __init plat_enable_iocoherency(void)
+{
+        int supported = 0;
+        if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
+                if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
+                        BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
+                        pr_info("Enabled Bonito CPU coherency\n");
+                        supported = 1;
+                }
+                if (strstr(fw_getcmdline(), "iobcuncached")) {
+                        BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
+                        BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
+                                ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
+                                  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
+                        pr_info("Disabled Bonito IOBC coherency\n");
+                } else {
+                        BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
+                        BONITO_PCIMEMBASECFG |=
+                                (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
+                                 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
+                        pr_info("Enabled Bonito IOBC coherency\n");
+                }
+        } else if (gcmp_niocu() != 0) {
+                /* Nothing special needs to be done to enable coherency */
+                pr_info("CMP IOCU detected\n");
+                if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) {
+                        pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
+                        return 0;
+                }
+                supported = 1;
+        }
+        hw_coherentio = supported;
+        return supported;
+}
+
+static void __init plat_setup_iocoherency(void)
+{
+#ifdef CONFIG_DMA_NONCOHERENT
+        /*
+         * Kernel has been configured with software coherency
+         * but we might choose to turn it off and use hardware
+         * coherency instead.
+         */
+        if (plat_enable_iocoherency()) {
+                if (coherentio == 0)
+                        pr_info("Hardware DMA cache coherency disabled\n");
+                else
+                        pr_info("Hardware DMA cache coherency enabled\n");
+        } else {
+                if (coherentio == 1)
+                        pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
+                else
+                        pr_info("Software DMA cache coherency enabled\n");
+        }
+#else
+        if (!plat_enable_iocoherency())
+                panic("Hardware DMA cache coherency not supported!");
+#endif
+}
+
 #ifdef CONFIG_BLK_DEV_IDE
 static void __init pci_clock_check(void)
 {
@@ -207,6 +268,8 @@ void __init plat_mem_setup(void)
         if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
                 bonito_quirks_setup();
 
+        plat_setup_iocoherency();
+
 #ifdef CONFIG_BLK_DEV_IDE
         pci_clock_check();
 #endif