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authorRalf Baechle <ralf@linux-mips.org>2007-07-09 11:29:16 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-07-10 12:33:05 -0400
commit688b3d720820a9e3e2e9d5882be64a28f649e206 (patch)
tree7181045ae55f69966e8237439a215242e9714ff4 /arch/mips/momentum
parentc99cabf034d42c9e4a9c1ed9dfd26411b2fb9b57 (diff)
[MIPS] Delete Ocelot 3 support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/momentum')
-rw-r--r--arch/mips/momentum/ocelot_3/Makefile8
-rw-r--r--arch/mips/momentum/ocelot_3/irq.c109
-rw-r--r--arch/mips/momentum/ocelot_3/ocelot_3_fpga.h59
-rw-r--r--arch/mips/momentum/ocelot_3/platform.c252
-rw-r--r--arch/mips/momentum/ocelot_3/prom.c189
-rw-r--r--arch/mips/momentum/ocelot_3/reset.c59
-rw-r--r--arch/mips/momentum/ocelot_3/setup.c398
7 files changed, 0 insertions, 1074 deletions
diff --git a/arch/mips/momentum/ocelot_3/Makefile b/arch/mips/momentum/ocelot_3/Makefile
deleted file mode 100644
index d5a090a85a15..000000000000
--- a/arch/mips/momentum/ocelot_3/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for Momentum Computer's Ocelot-3 board.
3#
4# Note! Dependencies are done automagically by 'make dep', which also
5# removes any old dependencies. DON'T put your own dependencies here
6# unless it's something special (ie not a .c file).
7#
8obj-y += irq.o platform.o prom.o reset.o setup.o
diff --git a/arch/mips/momentum/ocelot_3/irq.c b/arch/mips/momentum/ocelot_3/irq.c
deleted file mode 100644
index 3862d1d1add4..000000000000
--- a/arch/mips/momentum/ocelot_3/irq.c
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
9 *
10 * Copyright 2004 PMC-Sierra
11 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 *
33 * Copyright (C) 2004 MontaVista Software Inc.
34 * Author: Manish Lachwani, mlachwani@mvista.com
35 *
36 */
37#include <linux/errno.h>
38#include <linux/init.h>
39#include <linux/kernel_stat.h>
40#include <linux/module.h>
41#include <linux/signal.h>
42#include <linux/sched.h>
43#include <linux/types.h>
44#include <linux/interrupt.h>
45#include <linux/ioport.h>
46#include <linux/timex.h>
47#include <linux/slab.h>
48#include <linux/random.h>
49#include <asm/bitops.h>
50#include <asm/bootinfo.h>
51#include <asm/io.h>
52#include <asm/irq.h>
53#include <asm/mipsregs.h>
54#include <asm/system.h>
55
56static struct irqaction cascade_mv64340 = {
57 no_action, IRQF_DISABLED, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
58};
59
60void __init arch_init_irq(void)
61{
62 /*
63 * Clear all of the interrupts while we change the able around a bit.
64 * int-handler is not on bootstrap
65 */
66 clear_c0_status(ST0_IM | ST0_BEV);
67
68 rm7k_cpu_irq_init();
69
70 /* set up the cascading interrupts */
71 setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */
72 mv64340_irq_init(16);
73
74 set_c0_status(ST0_IM); /* IE in the status register */
75
76}
77
78asmlinkage void plat_irq_dispatch(void)
79{
80 unsigned int pending = read_c0_cause() & read_c0_status();
81
82 if (pending & STATUSF_IP0)
83 do_IRQ(0);
84 else if (pending & STATUSF_IP1)
85 do_IRQ(1);
86 else if (pending & STATUSF_IP2)
87 do_IRQ(2);
88 else if (pending & STATUSF_IP3)
89 do_IRQ(3);
90 else if (pending & STATUSF_IP4)
91 do_IRQ(4);
92 else if (pending & STATUSF_IP5)
93 do_IRQ(5);
94 else if (pending & STATUSF_IP6)
95 do_IRQ(6);
96 else if (pending & STATUSF_IP7)
97 do_IRQ(7);
98 else {
99 /*
100 * Now look at the extended interrupts
101 */
102 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
103
104 if (pending & STATUSF_IP8)
105 ll_mv64340_irq();
106 else
107 spurious_interrupt();
108 }
109}
diff --git a/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h b/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h
deleted file mode 100644
index 5710a9029f1c..000000000000
--- a/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * Ocelot-3 Board Register Definitions
3 *
4 * (C) 2002 Momentum Computer Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Louis Hamilton, Red Hat, Inc.
27 * hamilton@redhat.com [MIPS64 modifications]
28 *
29 * Copyright (C) 2004 MontaVista Software Inc.
30 * Author: Manish Lachwani, mlachwani@mvista.com
31 */
32
33#ifndef __OCELOT_3_FPGA_H__
34#define __OCELOT_3_FPGA_H__
35
36#define OCELOT_3_REG_BOARDREV 0x0
37#define OCELOT_3_REG_FPGA_REV 0x1
38#define OCELOT_3_REG_FPGA_TYPE 0x2
39#define OCELOT_3_REG_RESET_STATUS 0x3
40#define OCELOT_3_REG_BOARD_STATUS 0x4
41#define OCELOT_3_REG_CPCI_ID 0x5
42#define OCELOT_3_REG_SET 0x6
43#define OCELOT_3_REG_CLR 0x7
44#define OCELOT_3_REG_EEPROM_MODE 0x9
45#define OCELOT_3_REG_INTMASK 0xa
46#define OCELOT_3_REG_INTSTAT 0xb
47#define OCELOT_3_REG_UART_INTMASK 0xc
48#define OCELOT_3_REG_UART_INTSTAT 0xd
49#define OCELOT_3_REG_INTSET 0xe
50#define OCELOT_3_REG_INTCLR 0xf
51
52extern unsigned long ocelot_fpga_base;
53
54#define __FPGA_REG_TO_ADDR(reg) \
55 ((void *) ocelot_fpga_base + OCELOT_3_REG_##reg)
56#define OCELOT_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
57#define OCELOT_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
58
59#endif
diff --git a/arch/mips/momentum/ocelot_3/platform.c b/arch/mips/momentum/ocelot_3/platform.c
deleted file mode 100644
index cb63c82ef650..000000000000
--- a/arch/mips/momentum/ocelot_3/platform.c
+++ /dev/null
@@ -1,252 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006, 07 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2007 Dale Farnsworth (dale@farnsworth.org)
8 */
9#include <linux/delay.h>
10#include <linux/if_ether.h>
11#include <linux/init.h>
12#include <linux/ioport.h>
13#include <linux/module.h>
14#include <linux/mv643xx.h>
15#include <linux/platform_device.h>
16#include <linux/serial_8250.h>
17
18#include "ocelot_3_fpga.h"
19
20#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
21
22static struct resource mv643xx_eth_shared_resources[] = {
23 [0] = {
24 .name = "ethernet shared base",
25 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
26 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
27 MV643XX_ETH_SHARED_REGS_SIZE - 1,
28 .flags = IORESOURCE_MEM,
29 },
30};
31
32static struct platform_device mv643xx_eth_shared_device = {
33 .name = MV643XX_ETH_SHARED_NAME,
34 .id = 0,
35 .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
36 .resource = mv643xx_eth_shared_resources,
37};
38
39#define MV_SRAM_BASE 0xfe000000UL
40#define MV_SRAM_SIZE (256 * 1024)
41
42#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
43#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
44
45#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
46#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
47
48#define MV64x60_IRQ_ETH_0 48
49#define MV64x60_IRQ_ETH_1 49
50#define MV64x60_IRQ_ETH_2 50
51
52static struct resource mv64x60_eth0_resources[] = {
53 [0] = {
54 .name = "eth0 irq",
55 .start = MV64x60_IRQ_ETH_0,
56 .end = MV64x60_IRQ_ETH_0,
57 .flags = IORESOURCE_IRQ,
58 },
59};
60
61static struct mv643xx_eth_platform_data eth0_pd = {
62 .port_number = 0,
63
64 .tx_sram_addr = MV_SRAM_BASE_ETH0,
65 .tx_sram_size = MV_SRAM_TXRING_SIZE,
66 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
67
68 .rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
69 .rx_sram_size = MV_SRAM_RXRING_SIZE,
70 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
71};
72
73static struct platform_device eth0_device = {
74 .name = MV643XX_ETH_NAME,
75 .id = 0,
76 .num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
77 .resource = mv64x60_eth0_resources,
78 .dev = {
79 .platform_data = &eth0_pd,
80 },
81};
82
83static struct resource mv64x60_eth1_resources[] = {
84 [0] = {
85 .name = "eth1 irq",
86 .start = MV64x60_IRQ_ETH_1,
87 .end = MV64x60_IRQ_ETH_1,
88 .flags = IORESOURCE_IRQ,
89 },
90};
91
92static struct mv643xx_eth_platform_data eth1_pd = {
93 .port_number = 1,
94
95 .tx_sram_addr = MV_SRAM_BASE_ETH1,
96 .tx_sram_size = MV_SRAM_TXRING_SIZE,
97 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
98
99 .rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
100 .rx_sram_size = MV_SRAM_RXRING_SIZE,
101 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
102};
103
104static struct platform_device eth1_device = {
105 .name = MV643XX_ETH_NAME,
106 .id = 1,
107 .num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
108 .resource = mv64x60_eth1_resources,
109 .dev = {
110 .platform_data = &eth1_pd,
111 },
112};
113
114static struct resource mv64x60_eth2_resources[] = {
115 [0] = {
116 .name = "eth2 irq",
117 .start = MV64x60_IRQ_ETH_2,
118 .end = MV64x60_IRQ_ETH_2,
119 .flags = IORESOURCE_IRQ,
120 },
121};
122
123static struct mv643xx_eth_platform_data eth2_pd = {
124 .port_number = 2,
125};
126
127static struct platform_device eth2_device = {
128 .name = MV643XX_ETH_NAME,
129 .id = 2,
130 .num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
131 .resource = mv64x60_eth2_resources,
132 .dev = {
133 .platform_data = &eth2_pd,
134 },
135};
136
137static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
138 &mv643xx_eth_shared_device,
139 &eth0_device,
140 &eth1_device,
141 &eth2_device,
142};
143
144static u8 __init exchange_bit(u8 val, u8 cs)
145{
146 /* place the data */
147 OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
148 udelay(1);
149
150 /* turn the clock on */
151 OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
152 udelay(1);
153
154 /* turn the clock off and read-strobe */
155 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
156
157 /* return the data */
158 return (OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
159}
160
161static void __init get_mac(char dest[6])
162{
163 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
164 int i,j;
165
166 for (i = 0; i < 12; i++)
167 exchange_bit(read_opcode[i], 1);
168
169 for (j = 0; j < 6; j++) {
170 dest[j] = 0;
171 for (i = 0; i < 8; i++) {
172 dest[j] <<= 1;
173 dest[j] |= exchange_bit(0, 1);
174 }
175 }
176
177 /* turn off CS */
178 exchange_bit(0,0);
179}
180
181/*
182 * Copy and increment ethernet MAC address by a small value.
183 *
184 * This is useful for systems where the only one MAC address is stored in
185 * non-volatile memory for multiple ports.
186 */
187static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
188 unsigned int add)
189{
190 int i;
191
192 BUG_ON(add >= 256);
193
194 for (i = ETH_ALEN; i >= 0; i--) {
195 dst[i] = src[i] + add;
196 add = dst[i] < src[i]; /* compute carry */
197 }
198
199 WARN_ON(add);
200}
201
202static int __init mv643xx_eth_add_pds(void)
203{
204 unsigned char mac[ETH_ALEN];
205 int ret;
206
207 get_mac(mac);
208 eth_mac_add(eth0_pd.mac_addr, mac, 0);
209 eth_mac_add(eth1_pd.mac_addr, mac, 1);
210 eth_mac_add(eth2_pd.mac_addr, mac, 2);
211 ret = platform_add_devices(mv643xx_eth_pd_devs,
212 ARRAY_SIZE(mv643xx_eth_pd_devs));
213
214 return ret;
215}
216
217device_initcall(mv643xx_eth_add_pds);
218
219#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
220
221#define OCELOT3_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
222
223static struct plat_serial8250_port uart8250_data[] = {
224 {
225 .membase = (signed long) 0xfd000020,
226 .irq = 6,
227 .uartclk = 20000000,
228 .iotype = UPIO_MEM,
229 .flags = OCELOT3_UART_FLAGS,
230 .regshift = 2,
231 },
232 { },
233};
234
235static struct platform_device uart8250_device = {
236 .name = "serial8250",
237 .id = PLAT8250_DEV_PLATFORM,
238 .dev = {
239 .platform_data = uart8250_data,
240 },
241};
242
243static int __init uart8250_init(void)
244{
245 return platform_device_register(&uart8250_device);
246}
247
248module_init(uart8250_init);
249
250MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
251MODULE_LICENSE("GPL");
252MODULE_DESCRIPTION("8250 UART probe driver for the Ocelot 3");
diff --git a/arch/mips/momentum/ocelot_3/prom.c b/arch/mips/momentum/ocelot_3/prom.c
deleted file mode 100644
index 8e02df63578a..000000000000
--- a/arch/mips/momentum/ocelot_3/prom.c
+++ /dev/null
@@ -1,189 +0,0 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Louis Hamilton, Red Hat, Inc.
6 * hamilton@redhat.com [MIPS64 modifications]
7 *
8 * Copyright 2004 PMC-Sierra
9 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
10 *
11 * Based on Ocelot Linux port, which is
12 * Copyright 2001 MontaVista Software Inc.
13 * Author: jsun@mvista.com or jsun@junsun.net
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Copyright (C) 2004 MontaVista Software Inc.
21 * Author: Manish Lachwani, mlachwani@mvista.com
22 *
23 */
24#include <linux/init.h>
25#include <linux/bootmem.h>
26#include <linux/mv643xx.h>
27
28#include <asm/addrspace.h>
29#include <asm/bootinfo.h>
30#include <asm/pmon.h>
31#include "ocelot_3_fpga.h"
32
33struct callvectors* debug_vectors;
34extern unsigned long marvell_base;
35extern unsigned long cpu_clock;
36
37const char *get_system_type(void)
38{
39 return "Momentum Ocelot-3";
40}
41
42#ifdef CONFIG_64BIT
43
44unsigned long signext(unsigned long addr)
45{
46 addr &= 0xffffffff;
47 return (unsigned long)((int)addr);
48}
49
50void *get_arg(unsigned long args, int arc)
51{
52 unsigned long ul;
53 unsigned char *puc, uc;
54
55 args += (arc * 4);
56 ul = (unsigned long)signext(args);
57 puc = (unsigned char *)ul;
58 if (puc == 0)
59 return (void *)0;
60
61#ifdef CONFIG_CPU_LITTLE_ENDIAN
62 uc = *puc++;
63 ul = (unsigned long)uc;
64 uc = *puc++;
65 ul |= (((unsigned long)uc) << 8);
66 uc = *puc++;
67 ul |= (((unsigned long)uc) << 16);
68 uc = *puc++;
69 ul |= (((unsigned long)uc) << 24);
70#else /* CONFIG_CPU_LITTLE_ENDIAN */
71 uc = *puc++;
72 ul = ((unsigned long)uc) << 24;
73 uc = *puc++;
74 ul |= (((unsigned long)uc) << 16);
75 uc = *puc++;
76 ul |= (((unsigned long)uc) << 8);
77 uc = *puc++;
78 ul |= ((unsigned long)uc);
79#endif /* CONFIG_CPU_LITTLE_ENDIAN */
80 ul = signext(ul);
81 return (void *)ul;
82}
83
84char *arg64(unsigned long addrin, int arg_index)
85{
86 unsigned long args;
87 char *p;
88
89 args = signext(addrin);
90 p = (char *)get_arg(args, arg_index);
91
92 return p;
93}
94#endif /* CONFIG_64BIT */
95
96void __init prom_init(void)
97{
98 int argc = fw_arg0;
99 char **arg = (char **) fw_arg1;
100 char **env = (char **) fw_arg2;
101 struct callvectors *cv = (struct callvectors *) fw_arg3;
102 int i;
103
104#ifdef CONFIG_64BIT
105 char *ptr;
106 printk("prom_init - MIPS64\n");
107
108 /* save the PROM vectors for debugging use */
109 debug_vectors = (struct callvectors *)signext((unsigned long)cv);
110
111 /* arg[0] is "g", the rest is boot parameters */
112 arcs_cmdline[0] = '\0';
113
114 for (i = 1; i < argc; i++) {
115 ptr = (char *)arg64((unsigned long)arg, i);
116 if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
117 sizeof(arcs_cmdline))
118 break;
119 strcat(arcs_cmdline, ptr);
120 strcat(arcs_cmdline, " ");
121 }
122 i = 0;
123
124 while (1) {
125 ptr = (char *)arg64((unsigned long)env, i);
126 if (! ptr)
127 break;
128
129 if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
130 marvell_base = simple_strtol(ptr + strlen("gtbase="),
131 NULL, 16);
132
133 if ((marvell_base & 0xffffffff00000000) == 0)
134 marvell_base |= 0xffffffff00000000;
135
136 printk("marvell_base set to 0x%016lx\n", marvell_base);
137 }
138 if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
139 cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
140 NULL, 10);
141 printk("cpu_clock set to %d\n", cpu_clock);
142 }
143 i++;
144 }
145 printk("arcs_cmdline: %s\n", arcs_cmdline);
146
147#else /* CONFIG_64BIT */
148
149 /* save the PROM vectors for debugging use */
150 debug_vectors = cv;
151
152 /* arg[0] is "g", the rest is boot parameters */
153 arcs_cmdline[0] = '\0';
154 for (i = 1; i < argc; i++) {
155 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
156 >= sizeof(arcs_cmdline))
157 break;
158 strcat(arcs_cmdline, arg[i]);
159 strcat(arcs_cmdline, " ");
160 }
161
162 while (*env) {
163 if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
164 marvell_base = simple_strtol(*env + strlen("gtbase="),
165 NULL, 16);
166 }
167 if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
168 cpu_clock = simple_strtol(*env + strlen("cpuclock="),
169 NULL, 10);
170 }
171 env++;
172 }
173#endif /* CONFIG_64BIT */
174
175 mips_machgroup = MACH_GROUP_MOMENCO;
176 mips_machtype = MACH_MOMENCO_OCELOT_3;
177
178#ifndef CONFIG_64BIT
179 debug_vectors->printf("Booting Linux kernel...\n");
180#endif
181}
182
183void __init prom_free_prom_memory(void)
184{
185}
186
187void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
188{
189}
diff --git a/arch/mips/momentum/ocelot_3/reset.c b/arch/mips/momentum/ocelot_3/reset.c
deleted file mode 100644
index 9d86d2468376..000000000000
--- a/arch/mips/momentum/ocelot_3/reset.c
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 01, 05 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 * Copyright (C) 2002 Momentum Computer Inc.
12 * Author: Matthew Dharm <mdharm@momenco.com>
13 *
14 * Louis Hamilton, Red Hat, Inc.
15 * hamilton@redhat.com [MIPS64 modifications]
16 *
17 * Copyright 2004 PMC-Sierra
18 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
19 *
20 * Copyright (C) 2004 MontaVista Software Inc.
21 * Author: Manish Lachwani, mlachwani@mvista.com
22 */
23#include <linux/sched.h>
24#include <linux/mm.h>
25#include <linux/delay.h>
26#include <asm/io.h>
27#include <asm/pgtable.h>
28#include <asm/processor.h>
29#include <asm/reboot.h>
30#include <asm/system.h>
31
32void momenco_ocelot_restart(char *command)
33{
34 /* base address of timekeeper portion of part */
35 void *nvram = (void *) 0xfc807000L;
36
37 /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
38 writeb(0x84, nvram + 0xff7);
39
40 /* wait for the watchdog to go off */
41 mdelay(100+(1000/16));
42
43 /* if the watchdog fails for some reason, let people know */
44 printk(KERN_NOTICE "Watchdog reset failed\n");
45}
46
47void momenco_ocelot_halt(void)
48{
49 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
50 while (1)
51 __asm__(".set\tmips3\n\t"
52 "wait\n\t"
53 ".set\tmips0");
54}
55
56void momenco_ocelot_power_off(void)
57{
58 momenco_ocelot_halt();
59}
diff --git a/arch/mips/momentum/ocelot_3/setup.c b/arch/mips/momentum/ocelot_3/setup.c
deleted file mode 100644
index ff0829f81116..000000000000
--- a/arch/mips/momentum/ocelot_3/setup.c
+++ /dev/null
@@ -1,398 +0,0 @@
1/*
2 * setup.c
3 *
4 * BRIEF MODULE DESCRIPTION
5 * Momentum Computer Ocelot-3 board dependent boot routines
6 *
7 * Copyright (C) 1996, 1997, 01, 05 - 06 Ralf Baechle
8 * Copyright (C) 2000 RidgeRun, Inc.
9 * Copyright (C) 2001 Red Hat, Inc.
10 * Copyright (C) 2002 Momentum Computer
11 *
12 * Author: Matthew Dharm, Momentum Computer
13 * mdharm@momenco.com
14 *
15 * Louis Hamilton, Red Hat, Inc.
16 * hamilton@redhat.com [MIPS64 modifications]
17 *
18 * Author: RidgeRun, Inc.
19 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
20 *
21 * Copyright 2001 MontaVista Software Inc.
22 * Author: jsun@mvista.com or jsun@junsun.net
23 *
24 * Copyright 2004 PMC-Sierra
25 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
26 *
27 * Copyright (C) 2004 MontaVista Software Inc.
28 * Author: Manish Lachwani, mlachwani@mvista.com
29 *
30 * This program is free software; you can redistribute it and/or modify it
31 * under the terms of the GNU General Public License as published by the
32 * Free Software Foundation; either version 2 of the License, or (at your
33 * option) any later version.
34 *
35 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
36 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
37 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
38 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
40 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
41 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
42 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
44 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 * You should have received a copy of the GNU General Public License along
47 * with this program; if not, write to the Free Software Foundation, Inc.,
48 * 675 Mass Ave, Cambridge, MA 02139, USA.
49 */
50#include <linux/init.h>
51#include <linux/kernel.h>
52#include <linux/types.h>
53#include <linux/mc146818rtc.h>
54#include <linux/ioport.h>
55#include <linux/interrupt.h>
56#include <linux/pci.h>
57#include <linux/timex.h>
58#include <linux/bootmem.h>
59#include <linux/mv643xx.h>
60#include <linux/pm.h>
61#include <linux/bcd.h>
62
63#include <asm/time.h>
64#include <asm/page.h>
65#include <asm/bootinfo.h>
66#include <asm/io.h>
67#include <asm/irq.h>
68#include <asm/pci.h>
69#include <asm/processor.h>
70#include <asm/reboot.h>
71#include <asm/mc146818rtc.h>
72#include <asm/tlbflush.h>
73#include "ocelot_3_fpga.h"
74
75/* Marvell Discovery Register Base */
76unsigned long marvell_base = (signed)0xf4000000;
77
78/* CPU clock */
79unsigned long cpu_clock;
80
81/* RTC/NVRAM */
82unsigned char* rtc_base = (unsigned char*)(signed)0xfc800000;
83
84/* FPGA Base */
85unsigned long ocelot_fpga_base = (signed)0xfc000000;
86
87/* Serial base */
88unsigned long uart_base = (signed)0xfd000000;
89
90/*
91 * Marvell Discovery SRAM. This is one place where Ethernet
92 * Tx and Rx descriptors can be placed to improve performance
93 */
94extern unsigned long mv64340_sram_base;
95
96/* These functions are used for rebooting or halting the machine*/
97extern void momenco_ocelot_restart(char *command);
98extern void momenco_ocelot_halt(void);
99extern void momenco_ocelot_power_off(void);
100
101void momenco_time_init(void);
102static char reset_reason;
103
104void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
105 unsigned long entryhi, unsigned long pagemask);
106
107static inline unsigned long ENTRYLO(unsigned long paddr)
108{
109 return ((paddr & PAGE_MASK) |
110 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
111 _CACHE_UNCACHED)) >> 6;
112}
113
114void __init bus_error_init(void)
115{
116 /* nothing */
117}
118
119/*
120 * setup code for a handoff from a version 2 PMON 2000 PROM
121 */
122void setup_wired_tlb_entries(void)
123{
124 write_c0_wired(0);
125 local_flush_tlb_all();
126
127 /* marvell and extra space */
128 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), (signed)0xf4000000, PM_64K);
129
130 /* fpga, rtc, and uart */
131 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), (signed)0xfc000000, PM_16M);
132}
133
134unsigned long m48t37y_get_time(void)
135{
136 unsigned int year, month, day, hour, min, sec;
137 unsigned long flags;
138
139 spin_lock_irqsave(&rtc_lock, flags);
140 /* stop the update */
141 rtc_base[0x7ff8] = 0x40;
142
143 year = BCD2BIN(rtc_base[0x7fff]);
144 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
145
146 month = BCD2BIN(rtc_base[0x7ffe]);
147
148 day = BCD2BIN(rtc_base[0x7ffd]);
149
150 hour = BCD2BIN(rtc_base[0x7ffb]);
151 min = BCD2BIN(rtc_base[0x7ffa]);
152 sec = BCD2BIN(rtc_base[0x7ff9]);
153
154 /* start the update */
155 rtc_base[0x7ff8] = 0x00;
156 spin_unlock_irqrestore(&rtc_lock, flags);
157
158 return mktime(year, month, day, hour, min, sec);
159}
160
161int m48t37y_set_time(unsigned long sec)
162{
163 struct rtc_time tm;
164 unsigned long flags;
165
166 /* convert to a more useful format -- note months count from 0 */
167 to_tm(sec, &tm);
168 tm.tm_mon += 1;
169
170 spin_lock_irqsave(&rtc_lock, flags);
171 /* enable writing */
172 rtc_base[0x7ff8] = 0x80;
173
174 /* year */
175 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
176 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
177
178 /* month */
179 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
180
181 /* day */
182 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
183
184 /* hour/min/sec */
185 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
186 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
187 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
188
189 /* day of week -- not really used, but let's keep it up-to-date */
190 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
191
192 /* disable writing */
193 rtc_base[0x7ff8] = 0x00;
194 spin_unlock_irqrestore(&rtc_lock, flags);
195
196 return 0;
197}
198
199void __init plat_timer_setup(struct irqaction *irq)
200{
201 setup_irq(7, irq); /* Timer interrupt, unmask status IM7 */
202}
203
204void momenco_time_init(void)
205{
206 setup_wired_tlb_entries();
207
208 /*
209 * Ocelot-3 board has been built with both
210 * the Rm7900 and the Rm7065C
211 */
212 mips_hpt_frequency = cpu_clock / 2;
213
214 rtc_mips_get_time = m48t37y_get_time;
215 rtc_mips_set_time = m48t37y_set_time;
216}
217
218/*
219 * PCI Support for Ocelot-3
220 */
221
222/* Bus #0 IO and MEM space */
223#define OCELOT_3_PCI_IO_0_START 0xe0000000
224#define OCELOT_3_PCI_IO_0_SIZE 0x08000000
225#define OCELOT_3_PCI_MEM_0_START 0xc0000000
226#define OCELOT_3_PCI_MEM_0_SIZE 0x10000000
227
228/* Bus #1 IO and MEM space */
229#define OCELOT_3_PCI_IO_1_START 0xe8000000
230#define OCELOT_3_PCI_IO_1_SIZE 0x08000000
231#define OCELOT_3_PCI_MEM_1_START 0xd0000000
232#define OCELOT_3_PCI_MEM_1_SIZE 0x10000000
233
234static struct resource mv_pci_io_mem0_resource = {
235 .name = "MV64340 PCI0 IO MEM",
236 .start = OCELOT_3_PCI_IO_0_START,
237 .end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE - 1,
238 .flags = IORESOURCE_IO,
239};
240
241static struct resource mv_pci_io_mem1_resource = {
242 .name = "MV64340 PCI1 IO MEM",
243 .start = OCELOT_3_PCI_IO_1_START,
244 .end = OCELOT_3_PCI_IO_1_START + OCELOT_3_PCI_IO_1_SIZE - 1,
245 .flags = IORESOURCE_IO,
246};
247
248static struct resource mv_pci_mem0_resource = {
249 .name = "MV64340 PCI0 MEM",
250 .start = OCELOT_3_PCI_MEM_0_START,
251 .end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE - 1,
252 .flags = IORESOURCE_MEM,
253};
254
255static struct resource mv_pci_mem1_resource = {
256 .name = "MV64340 PCI1 MEM",
257 .start = OCELOT_3_PCI_MEM_1_START,
258 .end = OCELOT_3_PCI_MEM_1_START + OCELOT_3_PCI_MEM_1_SIZE - 1,
259 .flags = IORESOURCE_MEM,
260};
261
262static struct mv_pci_controller mv_bus0_controller = {
263 .pcic = {
264 .pci_ops = &mv_pci_ops,
265 .mem_resource = &mv_pci_mem0_resource,
266 .io_resource = &mv_pci_io_mem0_resource,
267 },
268 .config_addr = MV64340_PCI_0_CONFIG_ADDR,
269 .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
270};
271
272static struct mv_pci_controller mv_bus1_controller = {
273 .pcic = {
274 .pci_ops = &mv_pci_ops,
275 .mem_resource = &mv_pci_mem1_resource,
276 .io_resource = &mv_pci_io_mem1_resource,
277 },
278 .config_addr = MV64340_PCI_1_CONFIG_ADDR,
279 .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
280};
281
282static __init int __init ja_pci_init(void)
283{
284 uint32_t enable;
285 extern int pci_probe_only;
286
287 /* PMON will assign PCI resources */
288 pci_probe_only = 1;
289
290 enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
291 /*
292 * We require at least one enabled I/O or PCI memory window or we
293 * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
294 */
295 if (enable & (0x01 << 9) || enable & (0x01 << 10))
296 register_pci_controller(&mv_bus0_controller.pcic);
297
298 if (enable & (0x01 << 14) || enable & (0x01 << 15))
299 register_pci_controller(&mv_bus1_controller.pcic);
300
301 ioport_resource.end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE +
302 OCELOT_3_PCI_IO_1_SIZE - 1;
303
304 iomem_resource.end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE +
305 OCELOT_3_PCI_MEM_1_SIZE - 1;
306
307 set_io_port_base(OCELOT_3_PCI_IO_0_START); /* mips_io_port_base */
308
309 return 0;
310}
311
312arch_initcall(ja_pci_init);
313
314void __init plat_mem_setup(void)
315{
316 unsigned int tmpword;
317
318 board_time_init = momenco_time_init;
319
320 _machine_restart = momenco_ocelot_restart;
321 _machine_halt = momenco_ocelot_halt;
322 pm_power_off = momenco_ocelot_power_off;
323
324 /* Wired TLB entries */
325 setup_wired_tlb_entries();
326
327 /* shut down ethernet ports, just to be sure our memory doesn't get
328 * corrupted by random ethernet traffic.
329 */
330 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
331 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
332 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
333 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
334 do {}
335 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
336 do {}
337 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
338 do {}
339 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
340 do {}
341 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
342 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
343 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
344 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
345 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
346
347 /* Turn off the Bit-Error LED */
348 OCELOT_FPGA_WRITE(0x80, CLR);
349
350 tmpword = OCELOT_FPGA_READ(BOARDREV);
351 if (tmpword < 26)
352 printk("Momenco Ocelot-3: Board Assembly Rev. %c\n",
353 'A'+tmpword);
354 else
355 printk("Momenco Ocelot-3: Board Assembly Revision #0x%x\n",
356 tmpword);
357
358 tmpword = OCELOT_FPGA_READ(FPGA_REV);
359 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
360 tmpword = OCELOT_FPGA_READ(RESET_STATUS);
361 printk("Reset reason: 0x%x\n", tmpword);
362 switch (tmpword) {
363 case 0x1:
364 printk(" - Power-up reset\n");
365 break;
366 case 0x2:
367 printk(" - Push-button reset\n");
368 break;
369 case 0x4:
370 printk(" - cPCI bus reset\n");
371 break;
372 case 0x8:
373 printk(" - Watchdog reset\n");
374 break;
375 case 0x10:
376 printk(" - Software reset\n");
377 break;
378 default:
379 printk(" - Unknown reset cause\n");
380 }
381 reset_reason = tmpword;
382 OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
383
384 tmpword = OCELOT_FPGA_READ(CPCI_ID);
385 printk("cPCI ID register: 0x%02x\n", tmpword);
386 printk(" - Slot number: %d\n", tmpword & 0x1f);
387 printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
388 printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
389
390 tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
391 printk("Board Status register: 0x%02x\n", tmpword);
392 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
393 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
394 printk(" - L3 cache size: %d MB\n", (1<<((tmpword&12) >> 2))&~1);
395
396 /* Support for 128 MB memory */
397 add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM);
398}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 18:02:39 -0500