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authorFranck Bui-Huu <fbuihuu@gmail.com>2007-05-07 12:01:51 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-05-11 09:28:31 -0400
commit1e54f778af4467b816bf1289e7c4bf7e50067b7b (patch)
treec6b6daff71c7e26d59dc84a61fb05ff1fe3dac02 /arch/mips/momentum
parent0b6249567b4ecf6e9d5a8efcf149f3e7cf788cc0 (diff)
[MIPS] Remove Momenco Ocelot G support
Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/momentum')
-rw-r--r--arch/mips/momentum/ocelot_g/Makefile6
-rw-r--r--arch/mips/momentum/ocelot_g/dbg_io.c121
-rw-r--r--arch/mips/momentum/ocelot_g/gt-irq.c212
-rw-r--r--arch/mips/momentum/ocelot_g/irq.c101
-rw-r--r--arch/mips/momentum/ocelot_g/ocelot_pld.h30
-rw-r--r--arch/mips/momentum/ocelot_g/prom.c84
-rw-r--r--arch/mips/momentum/ocelot_g/reset.c47
-rw-r--r--arch/mips/momentum/ocelot_g/setup.c267
8 files changed, 0 insertions, 868 deletions
diff --git a/arch/mips/momentum/ocelot_g/Makefile b/arch/mips/momentum/ocelot_g/Makefile
deleted file mode 100644
index c0a0030d949d..000000000000
--- a/arch/mips/momentum/ocelot_g/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
1#
2# Makefile for Momentum Computer's Ocelot-G board.
3#
4
5obj-y += irq.o gt-irq.o prom.o reset.o setup.o
6obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/momentum/ocelot_g/dbg_io.c b/arch/mips/momentum/ocelot_g/dbg_io.c
deleted file mode 100644
index 32d6fb4ee679..000000000000
--- a/arch/mips/momentum/ocelot_g/dbg_io.c
+++ /dev/null
@@ -1,121 +0,0 @@
1
2#include <asm/serial.h> /* For the serial port location and base baud */
3
4/* --- CONFIG --- */
5
6typedef unsigned char uint8;
7typedef unsigned int uint32;
8
9/* --- END OF CONFIG --- */
10
11#define UART16550_BAUD_2400 2400
12#define UART16550_BAUD_4800 4800
13#define UART16550_BAUD_9600 9600
14#define UART16550_BAUD_19200 19200
15#define UART16550_BAUD_38400 38400
16#define UART16550_BAUD_57600 57600
17#define UART16550_BAUD_115200 115200
18
19#define UART16550_PARITY_NONE 0
20#define UART16550_PARITY_ODD 0x08
21#define UART16550_PARITY_EVEN 0x18
22#define UART16550_PARITY_MARK 0x28
23#define UART16550_PARITY_SPACE 0x38
24
25#define UART16550_DATA_5BIT 0x0
26#define UART16550_DATA_6BIT 0x1
27#define UART16550_DATA_7BIT 0x2
28#define UART16550_DATA_8BIT 0x3
29
30#define UART16550_STOP_1BIT 0x0
31#define UART16550_STOP_2BIT 0x4
32
33/* ----------------------------------------------------- */
34
35/* === CONFIG === */
36
37/* [jsun] we use the second serial port for kdb */
38#define BASE OCELOT_SERIAL1_BASE
39#define MAX_BAUD OCELOT_BASE_BAUD
40
41/* === END OF CONFIG === */
42
43#define REG_OFFSET 4
44
45/* register offset */
46#define OFS_RCV_BUFFER 0
47#define OFS_TRANS_HOLD 0
48#define OFS_SEND_BUFFER 0
49#define OFS_INTR_ENABLE (1*REG_OFFSET)
50#define OFS_INTR_ID (2*REG_OFFSET)
51#define OFS_DATA_FORMAT (3*REG_OFFSET)
52#define OFS_LINE_CONTROL (3*REG_OFFSET)
53#define OFS_MODEM_CONTROL (4*REG_OFFSET)
54#define OFS_RS232_OUTPUT (4*REG_OFFSET)
55#define OFS_LINE_STATUS (5*REG_OFFSET)
56#define OFS_MODEM_STATUS (6*REG_OFFSET)
57#define OFS_RS232_INPUT (6*REG_OFFSET)
58#define OFS_SCRATCH_PAD (7*REG_OFFSET)
59
60#define OFS_DIVISOR_LSB (0*REG_OFFSET)
61#define OFS_DIVISOR_MSB (1*REG_OFFSET)
62
63
64/* memory-mapped read/write of the port */
65#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
66#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
67
68void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
69{
70 /* disable interrupts */
71 UART16550_WRITE(OFS_INTR_ENABLE, 0);
72
73 /* set up baud rate */
74 {
75 uint32 divisor;
76
77 /* set DIAB bit */
78 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
79
80 /* set divisor */
81 divisor = MAX_BAUD / baud;
82 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
83 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
84
85 /* clear DIAB bit */
86 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
87 }
88
89 /* set data format */
90 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
91}
92
93static int remoteDebugInitialized = 0;
94
95uint8 getDebugChar(void)
96{
97 if (!remoteDebugInitialized) {
98 remoteDebugInitialized = 1;
99 debugInit(UART16550_BAUD_38400,
100 UART16550_DATA_8BIT,
101 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
102 }
103
104 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
105 return UART16550_READ(OFS_RCV_BUFFER);
106}
107
108
109int putDebugChar(uint8 byte)
110{
111 if (!remoteDebugInitialized) {
112 remoteDebugInitialized = 1;
113 debugInit(UART16550_BAUD_38400,
114 UART16550_DATA_8BIT,
115 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
116 }
117
118 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
119 UART16550_WRITE(OFS_SEND_BUFFER, byte);
120 return 1;
121}
diff --git a/arch/mips/momentum/ocelot_g/gt-irq.c b/arch/mips/momentum/ocelot_g/gt-irq.c
deleted file mode 100644
index e5576bd50fa9..000000000000
--- a/arch/mips/momentum/ocelot_g/gt-irq.c
+++ /dev/null
@@ -1,212 +0,0 @@
1/*
2 *
3 * Copyright 2002 Momentum Computer
4 * Author: mdharm@momenco.com
5 *
6 * arch/mips/momentum/ocelot_g/gt_irq.c
7 * Interrupt routines for gt64240. Currently it only handles timer irq.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/module.h>
15#include <linux/interrupt.h>
16#include <linux/kernel.h>
17#include <linux/sched.h>
18#include <linux/kernel_stat.h>
19#include <asm/gt64240.h>
20#include <asm/io.h>
21
22unsigned long bus_clock;
23
24/*
25 * These are interrupt handlers for the GT on-chip interrupts. They
26 * all come in to the MIPS on a single interrupt line, and have to
27 * be handled and ack'ed differently than other MIPS interrupts.
28 */
29
30#if 0
31
32struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];
33void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr);
34
35/*
36 * Hooks IRQ handler to the system. When the system is interrupted
37 * the interrupt service routine is called.
38 *
39 * Inputs :
40 * int_cause - The interrupt cause number. In EVB64120 two parameters
41 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
42 * bit_num - Indicates which bit number in the cause register
43 * isr_ptr - Pointer to the interrupt service routine
44 */
45void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr)
46{
47 irq_handlers[int_cause][bit_num].routine = isr_ptr;
48}
49
50
51/*
52 * Enables the IRQ on Galileo Chip
53 *
54 * Inputs :
55 * int_cause - The interrupt cause number. In EVB64120 two parameters
56 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
57 * bit_num - Indicates which bit number in the cause register
58 *
59 * Outputs :
60 * 1 if successful, 0 if failure
61 */
62int enable_galileo_irq(int int_cause, int bit_num)
63{
64 if (int_cause == INT_CAUSE_MAIN)
65 SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num));
66 else if (int_cause == INT_CAUSE_HIGH)
67 SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
68 (1 << bit_num));
69 else
70 return 0;
71
72 return 1;
73}
74
75/*
76 * Disables the IRQ on Galileo Chip
77 *
78 * Inputs :
79 * int_cause - The interrupt cause number. In EVB64120 two parameters
80 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
81 * bit_num - Indicates which bit number in the cause register
82 *
83 * Outputs :
84 * 1 if successful, 0 if failure
85 */
86int disable_galileo_irq(int int_cause, int bit_num)
87{
88 if (int_cause == INT_CAUSE_MAIN)
89 RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER,
90 (1 << bit_num));
91 else if (int_cause == INT_CAUSE_HIGH)
92 RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
93 (1 << bit_num));
94 else
95 return 0;
96 return 1;
97}
98#endif /* 0 */
99
100/*
101 * Interrupt handler for interrupts coming from the Galileo chip via P0_INT#.
102 *
103 * We route the timer interrupt to P0_INT# (IRQ 6), and that's all this
104 * routine can handle, for now.
105 *
106 * In the future, we'll route more interrupts to this pin, and that's why
107 * we keep this particular structure in the function.
108 */
109
110static irqreturn_t gt64240_p0int_irq(int irq, void *dev)
111{
112 uint32_t irq_src, irq_src_mask;
113 int handled;
114
115 /* get the low interrupt cause register */
116 irq_src = MV_READ(LOW_INTERRUPT_CAUSE_REGISTER);
117
118 /* get the mask register for this pin */
119 irq_src_mask = MV_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW);
120
121 /* mask off only the interrupts we're interested in */
122 irq_src = irq_src & irq_src_mask;
123
124 handled = IRQ_NONE;
125
126 /* Check for timer interrupt */
127 if (irq_src & 0x00000100) {
128 handled = IRQ_HANDLED;
129 irq_src &= ~0x00000100;
130
131 /* Clear any pending cause bits */
132 MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
133
134 /* handle the timer call */
135 do_timer(1);
136#ifndef CONFIG_SMP
137 update_process_times(user_mode(get_irq_regs()));
138#endif
139 }
140
141 if (irq_src) {
142 printk(KERN_INFO
143 "UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n",
144 irq_src);
145 }
146
147 return handled;
148}
149
150/*
151 * Initializes timer using galileo's built in timer.
152 */
153
154/*
155 * This will ignore the standard MIPS timer interrupt handler
156 * that is passed in as *irq (=irq0 in ../kernel/time.c).
157 * We will do our own timer interrupt handling.
158 */
159void gt64240_time_init(void)
160{
161 static struct irqaction timer;
162
163 /* Stop the timer -- we'll use timer #0 */
164 MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0);
165
166 /* Load timer value for 100 Hz */
167 MV_WRITE(TIMER_COUNTER0, bus_clock / 100);
168
169 /*
170 * Create the IRQ structure entry for the timer. Since we're too early
171 * in the boot process to use the "request_irq()" call, we'll hard-code
172 * the values to the correct interrupt line.
173 */
174 timer.handler = &gt64240_p0int_irq;
175 timer.flags = IRQF_SHARED | IRQF_DISABLED;
176 timer.name = "timer";
177 timer.dev_id = NULL;
178 timer.next = NULL;
179 timer.mask = CPU_MASK_NONE;
180 irq_desc[6].action = &timer;
181
182 enable_irq(6);
183
184 /* Clear any pending cause bits */
185 MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
186
187 /* Enable the interrupt for timer 0 */
188 MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1);
189
190 /* Enable the timer interrupt for GT-64240 pin P0_INT# */
191 MV_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100);
192
193 /* Configure and start the timer */
194 MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3);
195}
196
197void gt64240_irq_init(void)
198{
199#if 0
200 int i, j;
201
202 /* Reset irq handlers pointers to NULL */
203 for (i = 0; i < MAX_CAUSE_REGS; i++) {
204 for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) {
205 irq_handlers[i][j].next = NULL;
206 irq_handlers[i][j].sync = 0;
207 irq_handlers[i][j].routine = NULL;
208 irq_handlers[i][j].data = NULL;
209 }
210 }
211#endif /* 0 */
212}
diff --git a/arch/mips/momentum/ocelot_g/irq.c b/arch/mips/momentum/ocelot_g/irq.c
deleted file mode 100644
index 273541fe7087..000000000000
--- a/arch/mips/momentum/ocelot_g/irq.c
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 *
30 */
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/kernel_stat.h>
34#include <linux/module.h>
35#include <linux/signal.h>
36#include <linux/sched.h>
37#include <linux/types.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/timex.h>
41#include <linux/slab.h>
42#include <linux/random.h>
43#include <linux/bitops.h>
44#include <asm/bootinfo.h>
45#include <asm/io.h>
46#include <asm/irq.h>
47#include <asm/irq_cpu.h>
48#include <asm/mipsregs.h>
49#include <asm/system.h>
50
51asmlinkage void plat_irq_dispatch(void)
52{
53 unsigned int pending = read_c0_cause() & read_c0_status();
54
55 if (pending & STATUSF_IP2)
56 do_IRQ(2);
57 else if (pending & STATUSF_IP3)
58 do_IRQ(3);
59 else if (pending & STATUSF_IP4)
60 do_IRQ(4);
61 else if (pending & STATUSF_IP5)
62 do_IRQ(5);
63 else if (pending & STATUSF_IP6)
64 do_IRQ(6);
65 else if (pending & STATUSF_IP7)
66 do_IRQ(7);
67 else {
68 /*
69 * Now look at the extended interrupts
70 */
71 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
72
73 if (pending & STATUSF_IP8)
74 do_IRQ(8);
75 else if (pending & STATUSF_IP9)
76 do_IRQ(9);
77 else if (pending & STATUSF_IP10)
78 do_IRQ(10);
79 else if (pending & STATUSF_IP11)
80 do_IRQ(11);
81 else
82 spurious_interrupt();
83 }
84}
85
86extern void gt64240_irq_init(void);
87
88void __init arch_init_irq(void)
89{
90 /*
91 * Clear all of the interrupts while we change the able around a bit.
92 * int-handler is not on bootstrap
93 */
94 clear_c0_status(ST0_IM);
95 local_irq_disable();
96
97 mips_cpu_irq_init();
98 rm7k_cpu_irq_init();
99
100 gt64240_irq_init();
101}
diff --git a/arch/mips/momentum/ocelot_g/ocelot_pld.h b/arch/mips/momentum/ocelot_g/ocelot_pld.h
deleted file mode 100644
index 95e0534026d0..000000000000
--- a/arch/mips/momentum/ocelot_g/ocelot_pld.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Ocelot Board Register Definitions
3 *
4 * (C) 2001 Red Hat, Inc.
5 *
6 * GPL'd
7 */
8#ifndef __MOMENCO_OCELOT_PLD_H__
9#define __MOMENCO_OCELOT_PLD_H__
10
11#define OCELOT_CS0_ADDR (0xfc000000)
12
13#define OCELOT_REG_BOARDREV (0)
14#define OCELOT_REG_PLD1_ID (1)
15#define OCELOT_REG_PLD2_ID (2)
16#define OCELOT_REG_RESET_STATUS (3)
17#define OCELOT_REG_BOARD_STATUS (4)
18#define OCELOT_REG_CPCI_ID (5)
19#define OCELOT_REG_I2C_CTRL (8)
20#define OCELOT_REG_EEPROM_MODE (9)
21#define OCELOT_REG_INTMASK (10)
22#define OCELOT_REG_INTSTATUS (11)
23#define OCELOT_REG_INTSET (12)
24#define OCELOT_REG_INTCLR (13)
25
26#define __PLD_REG_TO_ADDR(reg) ((void *) OCELOT_CS0_ADDR + OCELOT_REG_##reg)
27#define OCELOT_PLD_WRITE(x, reg) writeb(x, __PLD_REG_TO_ADDR(reg))
28#define OCELOT_PLD_READ(reg) readb(__PLD_REG_TO_ADDR(reg))
29
30#endif /* __MOMENCO_OCELOT_PLD_H__ */
diff --git a/arch/mips/momentum/ocelot_g/prom.c b/arch/mips/momentum/ocelot_g/prom.c
deleted file mode 100644
index 836d0830720d..000000000000
--- a/arch/mips/momentum/ocelot_g/prom.c
+++ /dev/null
@@ -1,84 +0,0 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on Ocelot Linux port, which is
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: jsun@mvista.com or jsun@junsun.net
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/init.h>
15#include <linux/mm.h>
16#include <linux/sched.h>
17#include <linux/bootmem.h>
18
19#include <asm/addrspace.h>
20#include <asm/bootinfo.h>
21#include <asm/pmon.h>
22#include <asm/gt64240.h>
23
24#include "ocelot_pld.h"
25
26struct callvectors* debug_vectors;
27
28extern unsigned long marvell_base;
29extern unsigned long bus_clock;
30
31#ifdef CONFIG_GALILEO_GT64240_ETH
32extern unsigned char prom_mac_addr_base[6];
33#endif
34
35const char *get_system_type(void)
36{
37 return "Momentum Ocelot";
38}
39
40void __init prom_init(void)
41{
42 int argc = fw_arg0;
43 char **arg = (char **) fw_arg1;
44 char **env = (char **) fw_arg2;
45 struct callvectors *cv = (struct callvectors *) fw_arg3;
46 int i;
47
48 /* save the PROM vectors for debugging use */
49 debug_vectors = cv;
50
51 /* arg[0] is "g", the rest is boot parameters */
52 arcs_cmdline[0] = '\0';
53 for (i = 1; i < argc; i++) {
54 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
55 >= sizeof(arcs_cmdline))
56 break;
57 strcat(arcs_cmdline, arg[i]);
58 strcat(arcs_cmdline, " ");
59 }
60
61 mips_machgroup = MACH_GROUP_MOMENCO;
62 mips_machtype = MACH_MOMENCO_OCELOT_G;
63
64#ifdef CONFIG_GALILEO_GT64240_ETH
65 /* get the base MAC address for on-board ethernet ports */
66 memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6);
67#endif
68
69 while (*env) {
70 if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
71 marvell_base = simple_strtol(*env + strlen("gtbase="),
72 NULL, 16);
73 }
74 if (strncmp("busclock", *env, strlen("busclock")) == 0) {
75 bus_clock = simple_strtol(*env + strlen("busclock="),
76 NULL, 10);
77 }
78 env++;
79 }
80}
81
82void __init prom_free_prom_memory(void)
83{
84}
diff --git a/arch/mips/momentum/ocelot_g/reset.c b/arch/mips/momentum/ocelot_g/reset.c
deleted file mode 100644
index 3fd499adf4cf..000000000000
--- a/arch/mips/momentum/ocelot_g/reset.c
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 */
11#include <linux/sched.h>
12#include <linux/mm.h>
13#include <asm/io.h>
14#include <asm/pgtable.h>
15#include <asm/processor.h>
16#include <asm/reboot.h>
17#include <asm/system.h>
18#include <linux/delay.h>
19
20void momenco_ocelot_restart(char *command)
21{
22 void *nvram = ioremap_nocache(0x2c807000, 0x1000);
23
24 if (!nvram) {
25 printk(KERN_NOTICE "ioremap of reset register failed\n");
26 return;
27 }
28 writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to
29 assert reset in 1/16 second */
30 mdelay(10+(1000/16));
31 iounmap(nvram);
32 printk(KERN_NOTICE "Watchdog reset failed\n");
33}
34
35void momenco_ocelot_halt(void)
36{
37 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
38 while (1)
39 __asm__(".set\tmips3\n\t"
40 "wait\n\t"
41 ".set\tmips0");
42}
43
44void momenco_ocelot_power_off(void)
45{
46 momenco_ocelot_halt();
47}
diff --git a/arch/mips/momentum/ocelot_g/setup.c b/arch/mips/momentum/ocelot_g/setup.c
deleted file mode 100644
index 9db638a7982c..000000000000
--- a/arch/mips/momentum/ocelot_g/setup.c
+++ /dev/null
@@ -1,267 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Ocelot-G (CP7000G) - board dependent boot routines
4 *
5 * Copyright (C) 1996, 1997, 2001 Ralf Baechle
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
9 *
10 * Author: Matthew Dharm, Momentum Computer
11 * mdharm@momenco.com
12 *
13 * Author: RidgeRun, Inc.
14 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
15 *
16 * Copyright 2001 MontaVista Software Inc.
17 * Author: jsun@mvista.com or jsun@junsun.net
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
23 *
24 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
27 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
30 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * You should have received a copy of the GNU General Public License along
36 * with this program; if not, write to the Free Software Foundation, Inc.,
37 * 675 Mass Ave, Cambridge, MA 02139, USA.
38 *
39 */
40#include <linux/init.h>
41#include <linux/kernel.h>
42#include <linux/types.h>
43#include <linux/mm.h>
44#include <linux/swap.h>
45#include <linux/ioport.h>
46#include <linux/sched.h>
47#include <linux/interrupt.h>
48#include <linux/pci.h>
49#include <linux/pm.h>
50#include <linux/timex.h>
51#include <linux/vmalloc.h>
52
53#include <asm/time.h>
54#include <asm/bootinfo.h>
55#include <asm/page.h>
56#include <asm/io.h>
57#include <asm/gt64240.h>
58#include <asm/irq.h>
59#include <asm/pci.h>
60#include <asm/pgtable.h>
61#include <asm/processor.h>
62#include <asm/reboot.h>
63#include <linux/bootmem.h>
64
65#include "ocelot_pld.h"
66
67#ifdef CONFIG_GALILEO_GT64240_ETH
68extern unsigned char prom_mac_addr_base[6];
69#endif
70
71unsigned long marvell_base;
72
73/* These functions are used for rebooting or halting the machine*/
74extern void momenco_ocelot_restart(char *command);
75extern void momenco_ocelot_halt(void);
76extern void momenco_ocelot_power_off(void);
77
78extern void gt64240_time_init(void);
79extern void momenco_ocelot_irq_setup(void);
80
81static char reset_reason;
82
83static unsigned long ENTRYLO(unsigned long paddr)
84{
85 return ((paddr & PAGE_MASK) |
86 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
87 _CACHE_UNCACHED)) >> 6;
88}
89
90/* setup code for a handoff from a version 2 PMON 2000 PROM */
91void PMON_v2_setup(void)
92{
93 /* A wired TLB entry for the GT64240 and the serial port. The
94 GT64240 is going to be hit on every IRQ anyway - there's
95 absolutely no point in letting it be a random TLB entry, as
96 it'll just cause needless churning of the TLB. And we use
97 the other half for the serial port, which is just a PITA
98 otherwise :)
99
100 Device Physical Virtual
101 GT64240 Internal Regs 0xf4000000 0xe0000000
102 UARTs (CS2) 0xfd000000 0xe0001000
103 */
104 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
105 0xf4000000, PM_64K);
106 add_wired_entry(ENTRYLO(0xfd000000), ENTRYLO(0xfd001000),
107 0xfd000000, PM_4K);
108
109 /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
110 in the CS[012] region. We can't use ioremap() yet. The NVRAM
111 is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
112
113 Ocelot PLD (CS0) 0xfc000000 0xe0020000
114 NVRAM (CS1) 0xfc800000 0xe0030000
115 */
116 add_temporary_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfc010000),
117 0xfc000000, PM_64K);
118 add_temporary_entry(ENTRYLO(0xfc800000), ENTRYLO(0xfc810000),
119 0xfc800000, PM_64K);
120
121 marvell_base = 0xf4000000;
122}
123
124extern int rm7k_tcache_enabled;
125
126/*
127 * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
128 */
129#define Page_Invalidate_T 0x16
130static void __init setup_l3cache(unsigned long size)
131{
132 int register i;
133
134 printk("Enabling L3 cache...");
135
136 /* Enable the L3 cache in the GT64120A's CPU Configuration register */
137 MV_WRITE(0, MV_READ(0) | (1<<14));
138
139 /* Enable the L3 cache in the CPU */
140 set_c0_config(1<<12 /* CONF_TE */);
141
142 /* Clear the cache */
143 write_c0_taglo(0);
144 write_c0_taghi(0);
145
146 for (i=0; i < size; i+= 4096) {
147 __asm__ __volatile__ (
148 ".set noreorder\n\t"
149 ".set mips3\n\t"
150 "cache %1, (%0)\n\t"
151 ".set mips0\n\t"
152 ".set reorder"
153 :
154 : "r" (KSEG0ADDR(i)),
155 "i" (Page_Invalidate_T));
156 }
157
158 /* Let the RM7000 MM code know that the tertiary cache is enabled */
159 rm7k_tcache_enabled = 1;
160
161 printk("Done\n");
162}
163
164void __init plat_timer_setup(struct irqaction *irq)
165{
166}
167
168void __init plat_mem_setup(void)
169{
170 void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache);
171 unsigned int tmpword;
172
173 board_time_init = gt64240_time_init;
174
175 _machine_restart = momenco_ocelot_restart;
176 _machine_halt = momenco_ocelot_halt;
177 pm_power_off = momenco_ocelot_power_off;
178
179 /*
180 * initrd_start = (unsigned long)ocelot_initrd_start;
181 * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
182 * initrd_below_start_ok = 1;
183 */
184
185 /* do handoff reconfiguration */
186 PMON_v2_setup();
187
188#ifdef CONFIG_GALILEO_GT64240_ETH
189 /* get the mac addr */
190 memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6);
191#endif
192
193 /* Turn off the Bit-Error LED */
194 OCELOT_PLD_WRITE(0x80, INTCLR);
195
196 tmpword = OCELOT_PLD_READ(BOARDREV);
197 if (tmpword < 26)
198 printk("Momenco Ocelot-G: Board Assembly Rev. %c\n", 'A'+tmpword);
199 else
200 printk("Momenco Ocelot-G: Board Assembly Revision #0x%x\n", tmpword);
201
202 tmpword = OCELOT_PLD_READ(PLD1_ID);
203 printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
204 tmpword = OCELOT_PLD_READ(PLD2_ID);
205 printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
206 tmpword = OCELOT_PLD_READ(RESET_STATUS);
207 printk("Reset reason: 0x%x\n", tmpword);
208 reset_reason = tmpword;
209 OCELOT_PLD_WRITE(0xff, RESET_STATUS);
210
211 tmpword = OCELOT_PLD_READ(BOARD_STATUS);
212 printk("Board Status register: 0x%02x\n", tmpword);
213 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
214 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
215 printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
216 printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
217 printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
218
219 if (tmpword&12)
220 l3func((1<<(((tmpword&12) >> 2)+20)));
221
222 switch(tmpword &3) {
223 case 3:
224 /* 512MiB -- two banks of 256MiB */
225 add_memory_region( 0x0<<20, 0x100<<20, BOOT_MEM_RAM);
226/*
227 add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
228*/
229 break;
230 case 2:
231 /* 256MiB -- two banks of 128MiB */
232 add_memory_region( 0x0<<20, 0x80<<20, BOOT_MEM_RAM);
233 add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
234 break;
235 case 1:
236 /* 128MiB -- 64MiB per bank */
237 add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
238 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
239 break;
240 case 0:
241 /* 64MiB */
242 add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
243 break;
244 }
245
246 /* FIXME: Fix up the DiskOnChip mapping */
247 MV_WRITE(0x468, 0xfef73);
248}
249
250/* This needs to be one of the first initcalls, because no I/O port access
251 can work before this */
252
253static int io_base_ioremap(void)
254{
255 /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
256 unsigned long io_remap_range;
257
258 io_remap_range = (unsigned long) ioremap(0xc0000000, 0x30000000);
259 if (!io_remap_range)
260 panic("Could not ioremap I/O port range");
261
262 set_io_port_base(io_remap_range - 0xc0000000);
263
264 return 0;
265}
266
267module_init(io_base_ioremap);
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