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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2006-11-01 12:08:36 -0500
committerRalf Baechle <ralf@linux-mips.org>2006-11-29 20:14:46 -0500
commit1603b5aca4f15b34848fb5594d0c7b6333b99144 (patch)
tree79272aa41d6510b7256df62e287676885c3960cf /arch/mips/momentum
parentc87b6ebaea034c0e0ce86127870cf1511a307b64 (diff)
[MIPS] IRQ cleanups
This is a big irq cleanup patch. * Use set_irq_chip() to register irq_chip. * Initialize .mask, .unmask, .mask_ack field. Functions for these method are already exist in most case. * Do not initialize .startup, .shutdown, .enable, .disable fields if default routines provided by irq_chip_set_defaults() were suitable. * Remove redundant irq_desc initializations. * Remove unnecessary local_irq_save/local_irq_restore, spin_lock. With this cleanup, it would be easy to switch to slightly lightwait irq flow handlers (handle_level_irq(), etc.) instead of __do_IRQ(). Though whole this patch is quite large, changes in each irq_chip are not quite simple. Please review and test on your platform. Thanks. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/momentum')
-rw-r--r--arch/mips/momentum/ocelot_c/cpci-irq.c53
-rw-r--r--arch/mips/momentum/ocelot_c/uart-irq.c56
2 files changed, 12 insertions, 97 deletions
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
index 47e3fa32b075..7723f0998944 100644
--- a/arch/mips/momentum/ocelot_c/cpci-irq.c
+++ b/arch/mips/momentum/ocelot_c/cpci-irq.c
@@ -66,39 +66,6 @@ static inline void unmask_cpci_irq(unsigned int irq)
66} 66}
67 67
68/* 68/*
69 * Enables the IRQ in the FPGA
70 */
71static void enable_cpci_irq(unsigned int irq)
72{
73 unmask_cpci_irq(irq);
74}
75
76/*
77 * Initialize the IRQ in the FPGA
78 */
79static unsigned int startup_cpci_irq(unsigned int irq)
80{
81 unmask_cpci_irq(irq);
82 return 0;
83}
84
85/*
86 * Disables the IRQ in the FPGA
87 */
88static void disable_cpci_irq(unsigned int irq)
89{
90 mask_cpci_irq(irq);
91}
92
93/*
94 * Masks and ACKs an IRQ
95 */
96static void mask_and_ack_cpci_irq(unsigned int irq)
97{
98 mask_cpci_irq(irq);
99}
100
101/*
102 * End IRQ processing 69 * End IRQ processing
103 */ 70 */
104static void end_cpci_irq(unsigned int irq) 71static void end_cpci_irq(unsigned int irq)
@@ -125,15 +92,12 @@ void ll_cpci_irq(void)
125 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE); 92 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE);
126} 93}
127 94
128#define shutdown_cpci_irq disable_cpci_irq
129
130struct irq_chip cpci_irq_type = { 95struct irq_chip cpci_irq_type = {
131 .typename = "CPCI/FPGA", 96 .typename = "CPCI/FPGA",
132 .startup = startup_cpci_irq, 97 .ack = mask_cpci_irq,
133 .shutdown = shutdown_cpci_irq, 98 .mask = mask_cpci_irq,
134 .enable = enable_cpci_irq, 99 .mask_ack = mask_cpci_irq,
135 .disable = disable_cpci_irq, 100 .unmask = unmask_cpci_irq,
136 .ack = mask_and_ack_cpci_irq,
137 .end = end_cpci_irq, 101 .end = end_cpci_irq,
138}; 102};
139 103
@@ -141,11 +105,6 @@ void cpci_irq_init(void)
141{ 105{
142 int i; 106 int i;
143 107
144 /* Reset irq handlers pointers to NULL */ 108 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++)
145 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) { 109 set_irq_chip(i, &cpci_irq_type);
146 irq_desc[i].status = IRQ_DISABLED;
147 irq_desc[i].action = 0;
148 irq_desc[i].depth = 2;
149 irq_desc[i].chip = &cpci_irq_type;
150 }
151} 110}
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
index 510257dc205a..72faf81b36cc 100644
--- a/arch/mips/momentum/ocelot_c/uart-irq.c
+++ b/arch/mips/momentum/ocelot_c/uart-irq.c
@@ -60,39 +60,6 @@ static inline void unmask_uart_irq(unsigned int irq)
60} 60}
61 61
62/* 62/*
63 * Enables the IRQ in the FPGA
64 */
65static void enable_uart_irq(unsigned int irq)
66{
67 unmask_uart_irq(irq);
68}
69
70/*
71 * Initialize the IRQ in the FPGA
72 */
73static unsigned int startup_uart_irq(unsigned int irq)
74{
75 unmask_uart_irq(irq);
76 return 0;
77}
78
79/*
80 * Disables the IRQ in the FPGA
81 */
82static void disable_uart_irq(unsigned int irq)
83{
84 mask_uart_irq(irq);
85}
86
87/*
88 * Masks and ACKs an IRQ
89 */
90static void mask_and_ack_uart_irq(unsigned int irq)
91{
92 mask_uart_irq(irq);
93}
94
95/*
96 * End IRQ processing 63 * End IRQ processing
97 */ 64 */
98static void end_uart_irq(unsigned int irq) 65static void end_uart_irq(unsigned int irq)
@@ -118,28 +85,17 @@ void ll_uart_irq(void)
118 do_IRQ(ls1bit8(irq_src) + 74); 85 do_IRQ(ls1bit8(irq_src) + 74);
119} 86}
120 87
121#define shutdown_uart_irq disable_uart_irq
122
123struct irq_chip uart_irq_type = { 88struct irq_chip uart_irq_type = {
124 .typename = "UART/FPGA", 89 .typename = "UART/FPGA",
125 .startup = startup_uart_irq, 90 .ack = mask_uart_irq,
126 .shutdown = shutdown_uart_irq, 91 .mask = mask_uart_irq,
127 .enable = enable_uart_irq, 92 .mask_ack = mask_uart_irq,
128 .disable = disable_uart_irq, 93 .unmask = unmask_uart_irq,
129 .ack = mask_and_ack_uart_irq,
130 .end = end_uart_irq, 94 .end = end_uart_irq,
131}; 95};
132 96
133void uart_irq_init(void) 97void uart_irq_init(void)
134{ 98{
135 /* Reset irq handlers pointers to NULL */ 99 set_irq_chip(80, &uart_irq_type);
136 irq_desc[80].status = IRQ_DISABLED; 100 set_irq_chip(81, &uart_irq_type);
137 irq_desc[80].action = 0;
138 irq_desc[80].depth = 2;
139 irq_desc[80].chip = &uart_irq_type;
140
141 irq_desc[81].status = IRQ_DISABLED;
142 irq_desc[81].action = 0;
143 irq_desc[81].depth = 2;
144 irq_desc[81].chip = &uart_irq_type;
145} 101}