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authorFranck Bui-Huu <fbuihuu@gmail.com>2007-05-07 12:01:52 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-05-11 09:28:31 -0400
commitbef964e55ac128b1a6894c68171d0b22263449f8 (patch)
treef462bd850cbdc5273d6f0923350c694fc89e4abc /arch/mips/momentum
parent1e54f778af4467b816bf1289e7c4bf7e50067b7b (diff)
[MIPS] Remove Momenco Jaguar ATX support
It has some hackish code and it odd DMA results in the need to support old features in kernel code. Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/momentum')
-rw-r--r--arch/mips/momentum/Kconfig6
-rw-r--r--arch/mips/momentum/jaguar_atx/Makefile12
-rw-r--r--arch/mips/momentum/jaguar_atx/dbg_io.c125
-rw-r--r--arch/mips/momentum/jaguar_atx/irq.c94
-rw-r--r--arch/mips/momentum/jaguar_atx/ja-console.c101
-rw-r--r--arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h54
-rw-r--r--arch/mips/momentum/jaguar_atx/platform.c208
-rw-r--r--arch/mips/momentum/jaguar_atx/prom.c210
-rw-r--r--arch/mips/momentum/jaguar_atx/reset.c56
-rw-r--r--arch/mips/momentum/jaguar_atx/setup.c475
10 files changed, 0 insertions, 1341 deletions
diff --git a/arch/mips/momentum/Kconfig b/arch/mips/momentum/Kconfig
deleted file mode 100644
index 70a61cf7174d..000000000000
--- a/arch/mips/momentum/Kconfig
+++ /dev/null
@@ -1,6 +0,0 @@
1config JAGUAR_DMALOW
2 bool "Low DMA Mode"
3 depends on MOMENCO_JAGUAR_ATX
4 help
5 Select to Y if jump JP5 is set on your board, N otherwise. Normally
6 the jumper is set, so if you feel unsafe, just say Y.
diff --git a/arch/mips/momentum/jaguar_atx/Makefile b/arch/mips/momentum/jaguar_atx/Makefile
deleted file mode 100644
index 2e8cebd49bc0..000000000000
--- a/arch/mips/momentum/jaguar_atx/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
1#
2# Makefile for Momentum Computer's Jaguar-ATX board.
3#
4# Note! Dependencies are done automagically by 'make dep', which also
5# removes any old dependencies. DON'T put your own dependencies here
6# unless it's something special (ie not a .c file).
7#
8
9obj-y += irq.o platform.o prom.o reset.o setup.o
10
11obj-$(CONFIG_SERIAL_8250_CONSOLE) += ja-console.o
12obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
diff --git a/arch/mips/momentum/jaguar_atx/dbg_io.c b/arch/mips/momentum/jaguar_atx/dbg_io.c
deleted file mode 100644
index b85a6521f72d..000000000000
--- a/arch/mips/momentum/jaguar_atx/dbg_io.c
+++ /dev/null
@@ -1,125 +0,0 @@
1
2#if defined(CONFIG_REMOTE_DEBUG)
3
4#include <asm/serial.h> /* For the serial port location and base baud */
5
6/* --- CONFIG --- */
7
8typedef unsigned char uint8;
9typedef unsigned int uint32;
10
11/* --- END OF CONFIG --- */
12
13#define UART16550_BAUD_2400 2400
14#define UART16550_BAUD_4800 4800
15#define UART16550_BAUD_9600 9600
16#define UART16550_BAUD_19200 19200
17#define UART16550_BAUD_38400 38400
18#define UART16550_BAUD_57600 57600
19#define UART16550_BAUD_115200 115200
20
21#define UART16550_PARITY_NONE 0
22#define UART16550_PARITY_ODD 0x08
23#define UART16550_PARITY_EVEN 0x18
24#define UART16550_PARITY_MARK 0x28
25#define UART16550_PARITY_SPACE 0x38
26
27#define UART16550_DATA_5BIT 0x0
28#define UART16550_DATA_6BIT 0x1
29#define UART16550_DATA_7BIT 0x2
30#define UART16550_DATA_8BIT 0x3
31
32#define UART16550_STOP_1BIT 0x0
33#define UART16550_STOP_2BIT 0x4
34
35/* ----------------------------------------------------- */
36
37/* === CONFIG === */
38
39/* [jsun] we use the second serial port for kdb */
40#define BASE OCELOT_SERIAL1_BASE
41#define MAX_BAUD OCELOT_BASE_BAUD
42
43/* === END OF CONFIG === */
44
45#define REG_OFFSET 4
46
47/* register offset */
48#define OFS_RCV_BUFFER 0
49#define OFS_TRANS_HOLD 0
50#define OFS_SEND_BUFFER 0
51#define OFS_INTR_ENABLE (1*REG_OFFSET)
52#define OFS_INTR_ID (2*REG_OFFSET)
53#define OFS_DATA_FORMAT (3*REG_OFFSET)
54#define OFS_LINE_CONTROL (3*REG_OFFSET)
55#define OFS_MODEM_CONTROL (4*REG_OFFSET)
56#define OFS_RS232_OUTPUT (4*REG_OFFSET)
57#define OFS_LINE_STATUS (5*REG_OFFSET)
58#define OFS_MODEM_STATUS (6*REG_OFFSET)
59#define OFS_RS232_INPUT (6*REG_OFFSET)
60#define OFS_SCRATCH_PAD (7*REG_OFFSET)
61
62#define OFS_DIVISOR_LSB (0*REG_OFFSET)
63#define OFS_DIVISOR_MSB (1*REG_OFFSET)
64
65
66/* memory-mapped read/write of the port */
67#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
68#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
69
70void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
71{
72 /* disable interrupts */
73 UART16550_WRITE(OFS_INTR_ENABLE, 0);
74
75 /* set up baud rate */
76 {
77 uint32 divisor;
78
79 /* set DIAB bit */
80 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
81
82 /* set divisor */
83 divisor = MAX_BAUD / baud;
84 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
85 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
86
87 /* clear DIAB bit */
88 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
89 }
90
91 /* set data format */
92 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
93}
94
95static int remoteDebugInitialized = 0;
96
97uint8 getDebugChar(void)
98{
99 if (!remoteDebugInitialized) {
100 remoteDebugInitialized = 1;
101 debugInit(UART16550_BAUD_38400,
102 UART16550_DATA_8BIT,
103 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
104 }
105
106 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
107 return UART16550_READ(OFS_RCV_BUFFER);
108}
109
110
111int putDebugChar(uint8 byte)
112{
113 if (!remoteDebugInitialized) {
114 remoteDebugInitialized = 1;
115 debugInit(UART16550_BAUD_38400,
116 UART16550_DATA_8BIT,
117 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
118 }
119
120 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
121 UART16550_WRITE(OFS_SEND_BUFFER, byte);
122 return 1;
123}
124
125#endif
diff --git a/arch/mips/momentum/jaguar_atx/irq.c b/arch/mips/momentum/jaguar_atx/irq.c
deleted file mode 100644
index f2b432585df2..000000000000
--- a/arch/mips/momentum/jaguar_atx/irq.c
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * Copyright (C) 2002 Momentum Computer, Inc.
3 * Author: Matthew Dharm, mdharm@momenco.com
4 *
5 * Based on work by:
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Author: RidgeRun, Inc.
8 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
9 *
10 * Copyright 2001 MontaVista Software Inc.
11 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
12 *
13 * Copyright (C) 2000, 01, 06 Ralf Baechle (ralf@linux-mips.org)
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35#include <linux/init.h>
36#include <linux/interrupt.h>
37#include <linux/signal.h>
38#include <linux/types.h>
39#include <asm/irq_cpu.h>
40#include <asm/mipsregs.h>
41#include <asm/time.h>
42
43asmlinkage void plat_irq_dispatch(void)
44{
45 unsigned int pending = read_c0_cause() & read_c0_status();
46
47 if (pending & STATUSF_IP0)
48 do_IRQ(0);
49 else if (pending & STATUSF_IP1)
50 do_IRQ(1);
51 else if (pending & STATUSF_IP2)
52 do_IRQ(2);
53 else if (pending & STATUSF_IP3)
54 do_IRQ(3);
55 else if (pending & STATUSF_IP4)
56 do_IRQ(4);
57 else if (pending & STATUSF_IP5)
58 do_IRQ(5);
59 else if (pending & STATUSF_IP6)
60 do_IRQ(6);
61 else if (pending & STATUSF_IP7)
62 ll_timer_interrupt(7);
63 else {
64 /*
65 * Now look at the extended interrupts
66 */
67 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
68 if (pending & STATUSF_IP8)
69 ll_mv64340_irq();
70 }
71}
72
73static struct irqaction cascade_mv64340 = {
74 no_action, IRQF_DISABLED, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
75};
76
77void __init arch_init_irq(void)
78{
79 /*
80 * Clear all of the interrupts while we change the able around a bit.
81 * int-handler is not on bootstrap
82 */
83 clear_c0_status(ST0_IM);
84
85 mips_cpu_irq_init();
86 rm7k_cpu_irq_init();
87
88 /* set up the cascading interrupts */
89 setup_irq(8, &cascade_mv64340);
90
91 mv64340_irq_init(16);
92
93 set_c0_status(ST0_IM);
94}
diff --git a/arch/mips/momentum/jaguar_atx/ja-console.c b/arch/mips/momentum/jaguar_atx/ja-console.c
deleted file mode 100644
index 2c30b4f56245..000000000000
--- a/arch/mips/momentum/jaguar_atx/ja-console.c
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2001, 2002, 2004 Ralf Baechle
7 */
8#include <linux/init.h>
9#include <linux/console.h>
10#include <linux/kdev_t.h>
11#include <linux/major.h>
12#include <linux/termios.h>
13#include <linux/sched.h>
14#include <linux/tty.h>
15
16#include <linux/serial.h>
17#include <linux/serial_core.h>
18#include <asm/serial.h>
19
20/* SUPERIO uart register map */
21struct ja_uartregs {
22 union {
23 volatile u8 pad0[3];
24 volatile u8 rbr; /* read only, DLAB == 0 */
25 volatile u8 pad1[3];
26 volatile u8 thr; /* write only, DLAB == 0 */
27 volatile u8 pad2[3];
28 volatile u8 dll; /* DLAB == 1 */
29 } u1;
30 union {
31 volatile u8 pad0[3];
32 volatile u8 ier; /* DLAB == 0 */
33 volatile u8 pad1[3];
34 volatile u8 dlm; /* DLAB == 1 */
35 } u2;
36 union {
37 volatile u8 pad0[3];
38 volatile u8 iir; /* read only */
39 volatile u8 pad1[3];
40 volatile u8 fcr; /* write only */
41 } u3;
42 volatile u8 pad0[3];
43 volatile u8 iu_lcr;
44 volatile u8 pad1[3];
45 volatile u8 iu_mcr;
46 volatile u8 pad2[3];
47 volatile u8 iu_lsr;
48 volatile u8 pad3[3];
49 volatile u8 iu_msr;
50 volatile u8 pad4[3];
51 volatile u8 iu_scr;
52} ja_uregs_t;
53
54#define iu_rbr u1.rbr
55#define iu_thr u1.thr
56#define iu_dll u1.dll
57#define iu_ier u2.ier
58#define iu_dlm u2.dlm
59#define iu_iir u3.iir
60#define iu_fcr u3.fcr
61
62extern unsigned long uart_base;
63
64static inline struct ja_uartregs *console_uart(void)
65{
66 return (struct ja_uartregs *) (uart_base + 0x23UL);
67}
68
69void prom_putchar(char c)
70{
71 struct ja_uartregs *uart = console_uart();
72
73 while ((uart->iu_lsr & 0x20) == 0);
74 uart->iu_thr = c;
75}
76
77static void inline ja_console_probe(void)
78{
79 struct uart_port up;
80
81 /*
82 * Register to interrupt zero because we share the interrupt with
83 * the serial driver which we don't properly support yet.
84 */
85 memset(&up, 0, sizeof(up));
86 up.membase = (unsigned char *) uart_base + 0x23UL;
87 up.irq = JAGUAR_ATX_SERIAL1_IRQ;
88 up.uartclk = JAGUAR_ATX_UART_CLK;
89 up.regshift = 2;
90 up.iotype = UPIO_MEM;
91 up.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
92 up.line = 0;
93
94 if (early_serial_setup(&up))
95 printk(KERN_ERR "Early serial init of port 0 failed\n");
96}
97
98__init void ja_setup_console(void)
99{
100 ja_console_probe();
101}
diff --git a/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h b/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h
deleted file mode 100644
index 022f6974b76e..000000000000
--- a/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * Jaguar-ATX Board Register Definitions
3 *
4 * (C) 2002 Momentum Computer Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#ifndef __JAGUAR_ATX_FPGA_H__
27#define __JAGUAR_ATX_FPGA_H__
28
29#define JAGUAR_ATX_REG_BOARDREV 0x0
30#define JAGUAR_ATX_REG_FPGA_REV 0x1
31#define JAGUAR_ATX_REG_FPGA_TYPE 0x2
32#define JAGUAR_ATX_REG_RESET_STATUS 0x3
33#define JAGUAR_ATX_REG_BOARD_STATUS 0x4
34#define JAGUAR_ATX_REG_RESERVED1 0x5
35#define JAGUAR_ATX_REG_SET 0x6
36#define JAGUAR_ATX_REG_CLR 0x7
37#define JAGUAR_ATX_REG_EEPROM_MODE 0x9
38#define JAGUAR_ATX_REG_RESERVED2 0xa
39#define JAGUAR_ATX_REG_RESERVED3 0xb
40#define JAGUAR_ATX_REG_RESERVED4 0xc
41#define JAGUAR_ATX_REG_PHY_INTSTAT 0xd
42#define JAGUAR_ATX_REG_RESERVED5 0xe
43#define JAGUAR_ATX_REG_RESERVED6 0xf
44
45#define JAGUAR_ATX_CS0_ADDR 0xfc000000L
46
47extern unsigned long ja_fpga_base;
48
49#define __FPGA_REG_TO_ADDR(reg) \
50 ((void *) ja_fpga_base + JAGUAR_ATX_REG_##reg)
51#define JAGUAR_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
52#define JAGUAR_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
53
54#endif
diff --git a/arch/mips/momentum/jaguar_atx/platform.c b/arch/mips/momentum/jaguar_atx/platform.c
deleted file mode 100644
index 561844878a90..000000000000
--- a/arch/mips/momentum/jaguar_atx/platform.c
+++ /dev/null
@@ -1,208 +0,0 @@
1#include <linux/delay.h>
2#include <linux/if_ether.h>
3#include <linux/ioport.h>
4#include <linux/mv643xx.h>
5#include <linux/platform_device.h>
6
7#include "jaguar_atx_fpga.h"
8
9#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
10
11static struct resource mv643xx_eth_shared_resources[] = {
12 [0] = {
13 .name = "ethernet shared base",
14 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
15 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
16 MV643XX_ETH_SHARED_REGS_SIZE - 1,
17 .flags = IORESOURCE_MEM,
18 },
19};
20
21static struct platform_device mv643xx_eth_shared_device = {
22 .name = MV643XX_ETH_SHARED_NAME,
23 .id = 0,
24 .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
25 .resource = mv643xx_eth_shared_resources,
26};
27
28#define MV_SRAM_BASE 0xfe000000UL
29#define MV_SRAM_SIZE (256 * 1024)
30
31#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
32#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
33
34#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
35#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
36
37#define MV64x60_IRQ_ETH_0 48
38#define MV64x60_IRQ_ETH_1 49
39#define MV64x60_IRQ_ETH_2 50
40
41static struct resource mv64x60_eth0_resources[] = {
42 [0] = {
43 .name = "eth0 irq",
44 .start = MV64x60_IRQ_ETH_0,
45 .end = MV64x60_IRQ_ETH_0,
46 .flags = IORESOURCE_IRQ,
47 },
48};
49
50static struct mv643xx_eth_platform_data eth0_pd = {
51 .port_number = 0,
52
53 .tx_sram_addr = MV_SRAM_BASE_ETH0,
54 .tx_sram_size = MV_SRAM_TXRING_SIZE,
55 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
56
57 .rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
58 .rx_sram_size = MV_SRAM_RXRING_SIZE,
59 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
60};
61
62static struct platform_device eth0_device = {
63 .name = MV643XX_ETH_NAME,
64 .id = 0,
65 .num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
66 .resource = mv64x60_eth0_resources,
67 .dev = {
68 .platform_data = &eth0_pd,
69 },
70};
71
72static struct resource mv64x60_eth1_resources[] = {
73 [0] = {
74 .name = "eth1 irq",
75 .start = MV64x60_IRQ_ETH_1,
76 .end = MV64x60_IRQ_ETH_1,
77 .flags = IORESOURCE_IRQ,
78 },
79};
80
81static struct mv643xx_eth_platform_data eth1_pd = {
82 .port_number = 1,
83
84 .tx_sram_addr = MV_SRAM_BASE_ETH1,
85 .tx_sram_size = MV_SRAM_TXRING_SIZE,
86 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
87
88 .rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
89 .rx_sram_size = MV_SRAM_RXRING_SIZE,
90 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
91};
92
93static struct platform_device eth1_device = {
94 .name = MV643XX_ETH_NAME,
95 .id = 1,
96 .num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
97 .resource = mv64x60_eth1_resources,
98 .dev = {
99 .platform_data = &eth1_pd,
100 },
101};
102
103static struct resource mv64x60_eth2_resources[] = {
104 [0] = {
105 .name = "eth2 irq",
106 .start = MV64x60_IRQ_ETH_2,
107 .end = MV64x60_IRQ_ETH_2,
108 .flags = IORESOURCE_IRQ,
109 },
110};
111
112static struct mv643xx_eth_platform_data eth2_pd = {
113 .port_number = 2,
114};
115
116static struct platform_device eth2_device = {
117 .name = MV643XX_ETH_NAME,
118 .id = 2,
119 .num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
120 .resource = mv64x60_eth2_resources,
121 .dev = {
122 .platform_data = &eth2_pd,
123 },
124};
125
126static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
127 &mv643xx_eth_shared_device,
128 &eth0_device,
129 &eth1_device,
130 &eth2_device,
131};
132
133static u8 __init exchange_bit(u8 val, u8 cs)
134{
135 /* place the data */
136 JAGUAR_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
137 udelay(1);
138
139 /* turn the clock on */
140 JAGUAR_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
141 udelay(1);
142
143 /* turn the clock off and read-strobe */
144 JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
145
146 /* return the data */
147 return (JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
148}
149
150static void __init get_mac(char dest[6])
151{
152 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
153 int i,j;
154
155 for (i = 0; i < 12; i++)
156 exchange_bit(read_opcode[i], 1);
157
158 for (j = 0; j < 6; j++) {
159 dest[j] = 0;
160 for (i = 0; i < 8; i++) {
161 dest[j] <<= 1;
162 dest[j] |= exchange_bit(0, 1);
163 }
164 }
165
166 /* turn off CS */
167 exchange_bit(0,0);
168}
169
170/*
171 * Copy and increment ethernet MAC address by a small value.
172 *
173 * This is useful for systems where the only one MAC address is stored in
174 * non-volatile memory for multiple ports.
175 */
176static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
177 unsigned int add)
178{
179 int i;
180
181 BUG_ON(add >= 256);
182
183 for (i = ETH_ALEN; i >= 0; i--) {
184 dst[i] = src[i] + add;
185 add = dst[i] < src[i]; /* compute carry */
186 }
187
188 WARN_ON(add);
189}
190
191static int __init mv643xx_eth_add_pds(void)
192{
193 unsigned char mac[ETH_ALEN];
194 int ret;
195
196 get_mac(mac);
197 eth_mac_add(eth0_pd.mac_addr, mac, 0);
198 eth_mac_add(eth1_pd.mac_addr, mac, 1);
199 eth_mac_add(eth2_pd.mac_addr, mac, 2);
200 ret = platform_add_devices(mv643xx_eth_pd_devs,
201 ARRAY_SIZE(mv643xx_eth_pd_devs));
202
203 return ret;
204}
205
206device_initcall(mv643xx_eth_add_pds);
207
208#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
diff --git a/arch/mips/momentum/jaguar_atx/prom.c b/arch/mips/momentum/jaguar_atx/prom.c
deleted file mode 100644
index 5dd154ee58f6..000000000000
--- a/arch/mips/momentum/jaguar_atx/prom.c
+++ /dev/null
@@ -1,210 +0,0 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Louis Hamilton, Red Hat, Inc.
6 * hamilton@redhat.com [MIPS64 modifications]
7 *
8 * Based on Ocelot Linux port, which is
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: jsun@mvista.com or jsun@junsun.net
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * Added changes for SMP - Manish Lachwani (lachwani@pmc-sierra.com)
18 */
19#include <linux/init.h>
20#include <linux/mm.h>
21#include <linux/sched.h>
22#include <linux/bootmem.h>
23#include <linux/mv643xx.h>
24
25#include <asm/addrspace.h>
26#include <asm/bootinfo.h>
27#include <asm/pmon.h>
28
29#include "jaguar_atx_fpga.h"
30
31extern void ja_setup_console(void);
32
33struct callvectors *debug_vectors;
34
35extern unsigned long cpu_clock;
36
37const char *get_system_type(void)
38{
39 return "Momentum Jaguar-ATX";
40}
41
42#ifdef CONFIG_64BIT
43
44unsigned long signext(unsigned long addr)
45{
46 addr &= 0xffffffff;
47 return (unsigned long)((int)addr);
48}
49
50void *get_arg(unsigned long args, int arc)
51{
52 unsigned long ul;
53 unsigned char *puc, uc;
54
55 args += (arc * 4);
56 ul = (unsigned long)signext(args);
57 puc = (unsigned char *)ul;
58 if (puc == 0)
59 return (void *)0;
60
61#ifdef CONFIG_CPU_LITTLE_ENDIAN
62 uc = *puc++;
63 l = (unsigned long)uc;
64 uc = *puc++;
65 ul |= (((unsigned long)uc) << 8);
66 uc = *puc++;
67 ul |= (((unsigned long)uc) << 16);
68 uc = *puc++;
69 ul |= (((unsigned long)uc) << 24);
70#else
71 uc = *puc++;
72 ul = ((unsigned long)uc) << 24;
73 uc = *puc++;
74 ul |= (((unsigned long)uc) << 16);
75 uc = *puc++;
76 ul |= (((unsigned long)uc) << 8);
77 uc = *puc++;
78 ul |= ((unsigned long)uc);
79#endif
80 ul = signext(ul);
81
82 return (void *)ul;
83}
84
85char *arg64(unsigned long addrin, int arg_index)
86{
87 unsigned long args;
88 char *p;
89
90 args = signext(addrin);
91 p = (char *)get_arg(args, arg_index);
92
93 return p;
94}
95#endif /* CONFIG_64BIT */
96
97/* PMON passes arguments in C main() style */
98void __init prom_init(void)
99{
100 int argc = fw_arg0;
101 char **arg = (char **) fw_arg1;
102 char **env = (char **) fw_arg2;
103 struct callvectors *cv = (struct callvectors *) fw_arg3;
104 int i;
105
106#ifdef CONFIG_SERIAL_8250_CONSOLE
107// ja_setup_console(); /* The very first thing. */
108#endif
109
110#ifdef CONFIG_64BIT
111 char *ptr;
112
113 printk("Mips64 Jaguar-ATX\n");
114 /* save the PROM vectors for debugging use */
115 debug_vectors = (struct callvectors *)signext((unsigned long)cv);
116
117 /* arg[0] is "g", the rest is boot parameters */
118 arcs_cmdline[0] = '\0';
119
120 for (i = 1; i < argc; i++) {
121 ptr = (char *)arg64((unsigned long)arg, i);
122 if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
123 sizeof(arcs_cmdline))
124 break;
125 strcat(arcs_cmdline, ptr);
126 strcat(arcs_cmdline, " ");
127 }
128
129 i = 0;
130 while (1) {
131 ptr = (char *)arg64((unsigned long)env, i);
132 if (! ptr)
133 break;
134
135 if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
136 marvell_base = simple_strtol(ptr + strlen("gtbase="),
137 NULL, 16);
138
139 if ((marvell_base & 0xffffffff00000000) == 0)
140 marvell_base |= 0xffffffff00000000;
141
142 printk("marvell_base set to 0x%016lx\n", marvell_base);
143 }
144 if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
145 cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
146 NULL, 10);
147 printk("cpu_clock set to %d\n", cpu_clock);
148 }
149 i++;
150 }
151 printk("arcs_cmdline: %s\n", arcs_cmdline);
152
153#else /* CONFIG_64BIT */
154 /* save the PROM vectors for debugging use */
155 debug_vectors = cv;
156
157 /* arg[0] is "g", the rest is boot parameters */
158 arcs_cmdline[0] = '\0';
159 for (i = 1; i < argc; i++) {
160 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
161 >= sizeof(arcs_cmdline))
162 break;
163 strcat(arcs_cmdline, arg[i]);
164 strcat(arcs_cmdline, " ");
165 }
166
167 while (*env) {
168 if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
169 marvell_base = simple_strtol(*env + strlen("gtbase="),
170 NULL, 16);
171 }
172 if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
173 cpu_clock = simple_strtol(*env + strlen("cpuclock="),
174 NULL, 10);
175 }
176 env++;
177 }
178#endif /* CONFIG_64BIT */
179 mips_machgroup = MACH_GROUP_MOMENCO;
180 mips_machtype = MACH_MOMENCO_JAGUAR_ATX;
181}
182
183void __init prom_free_prom_memory(void)
184{
185}
186
187void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
188{
189}
190
191int prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp)
192{
193 /* Clear the semaphore */
194 *(volatile uint32_t *)(0xbb000a68) = 0x80000000;
195
196 return 1;
197}
198
199void prom_init_secondary(void)
200{
201 clear_c0_config(CONF_CM_CMASK);
202 set_c0_config(0x2);
203
204 clear_c0_status(ST0_IM);
205 set_c0_status(0x1ffff);
206}
207
208void prom_smp_finish(void)
209{
210}
diff --git a/arch/mips/momentum/jaguar_atx/reset.c b/arch/mips/momentum/jaguar_atx/reset.c
deleted file mode 100644
index c73b0897dc52..000000000000
--- a/arch/mips/momentum/jaguar_atx/reset.c
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 * Copyright (C) 2002 Momentum Computer Inc.
12 * Author: Matthew Dharm <mdharm@momenco.com>
13 *
14 * Louis Hamilton, Red Hat, Inc.
15 * hamilton@redhat.com [MIPS64 modifications]
16 */
17#include <linux/sched.h>
18#include <linux/mm.h>
19#include <asm/io.h>
20#include <asm/pgtable.h>
21#include <asm/processor.h>
22#include <asm/reboot.h>
23#include <asm/system.h>
24#include <linux/delay.h>
25
26void momenco_jaguar_restart(char *command)
27{
28 /* base address of timekeeper portion of part */
29#ifdef CONFIG_64BIT
30 void *nvram = (void*) 0xfffffffffc807000;
31#else
32 void *nvram = (void*) 0xfc807000;
33#endif
34 /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
35 writeb(0x84, nvram + 0xff7);
36
37 /* wait for the watchdog to go off */
38 mdelay(100+(1000/16));
39
40 /* if the watchdog fails for some reason, let people know */
41 printk(KERN_NOTICE "Watchdog reset failed\n");
42}
43
44void momenco_jaguar_halt(void)
45{
46 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
47 while (1)
48 __asm__(".set\tmips3\n\t"
49 "wait\n\t"
50 ".set\tmips0");
51}
52
53void momenco_jaguar_power_off(void)
54{
55 momenco_jaguar_halt();
56}
diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c
deleted file mode 100644
index 5a510142b978..000000000000
--- a/arch/mips/momentum/jaguar_atx/setup.c
+++ /dev/null
@@ -1,475 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Jaguar-ATX board dependent boot routines
4 *
5 * Copyright (C) 1996, 1997, 2001, 04, 06 Ralf Baechle (ralf@linux-mips.org)
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
9 *
10 * Author: Matthew Dharm, Momentum Computer
11 * mdharm@momenco.com
12 *
13 * Louis Hamilton, Red Hat, Inc.
14 * hamilton@redhat.com [MIPS64 modifications]
15 *
16 * Author: RidgeRun, Inc.
17 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
18 *
19 * Copyright 2001 MontaVista Software Inc.
20 * Author: jsun@mvista.com or jsun@junsun.net
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License as published by the
24 * Free Software Foundation; either version 2 of the License, or (at your
25 * option) any later version.
26 *
27 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
30 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
33 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * You should have received a copy of the GNU General Public License along
39 * with this program; if not, write to the Free Software Foundation, Inc.,
40 * 675 Mass Ave, Cambridge, MA 02139, USA.
41 */
42#include <linux/bcd.h>
43#include <linux/init.h>
44#include <linux/kernel.h>
45#include <linux/types.h>
46#include <linux/mm.h>
47#include <linux/bootmem.h>
48#include <linux/module.h>
49#include <linux/pci.h>
50#include <linux/swap.h>
51#include <linux/ioport.h>
52#include <linux/pm.h>
53#include <linux/sched.h>
54#include <linux/interrupt.h>
55#include <linux/timex.h>
56#include <linux/vmalloc.h>
57#include <linux/mv643xx.h>
58
59#include <asm/time.h>
60#include <asm/bootinfo.h>
61#include <asm/page.h>
62#include <asm/io.h>
63#include <asm/irq.h>
64#include <asm/processor.h>
65#include <asm/reboot.h>
66#include <asm/tlbflush.h>
67
68#include "jaguar_atx_fpga.h"
69
70extern unsigned long mv64340_sram_base;
71unsigned long cpu_clock;
72
73/* These functions are used for rebooting or halting the machine*/
74extern void momenco_jaguar_restart(char *command);
75extern void momenco_jaguar_halt(void);
76extern void momenco_jaguar_power_off(void);
77
78void momenco_time_init(void);
79
80static char reset_reason;
81
82static inline unsigned long ENTRYLO(unsigned long paddr)
83{
84 return ((paddr & PAGE_MASK) |
85 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
86 _CACHE_UNCACHED)) >> 6;
87}
88
89void __init bus_error_init(void) { /* nothing */ }
90
91/*
92 * Load a few TLB entries for the MV64340 and perhiperals. The MV64340 is going
93 * to be hit on every IRQ anyway - there's absolutely no point in letting it be
94 * a random TLB entry, as it'll just cause needless churning of the TLB. And we
95 * use the other half for the serial port, which is just a PITA otherwise :)
96 *
97 * Device Physical Virtual
98 * MV64340 Internal Regs 0xf4000000 0xf4000000
99 * Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
100 * NVRAM (CS1) 0xfc800000 0xfc800000
101 * UARTs (CS2) 0xfd000000 0xfd000000
102 * Internal SRAM 0xfe000000 0xfe000000
103 * M-Systems DOC (CS3) 0xff000000 0xff000000
104 */
105
106static __init void wire_stupidity_into_tlb(void)
107{
108#ifdef CONFIG_32BIT
109 write_c0_wired(0);
110 local_flush_tlb_all();
111
112 /* marvell and extra space */
113 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
114 0xf4000000UL, PM_64K);
115 /* fpga, rtc, and uart */
116 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000),
117 0xfc000000UL, PM_16M);
118// /* m-sys and internal SRAM */
119// add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000),
120// 0xfe000000UL, PM_16M);
121
122 marvell_base = 0xf4000000;
123 //mv64340_sram_base = 0xfe000000; /* Currently unused */
124#endif
125}
126
127unsigned long marvell_base = 0xf4000000L;
128unsigned long ja_fpga_base = JAGUAR_ATX_CS0_ADDR;
129unsigned long uart_base = 0xfd000000L;
130static unsigned char *rtc_base = (unsigned char*) 0xfc800000L;
131
132EXPORT_SYMBOL(marvell_base);
133
134static __init int per_cpu_mappings(void)
135{
136 marvell_base = (unsigned long) ioremap(0xf4000000, 0x10000);
137 ja_fpga_base = (unsigned long) ioremap(JAGUAR_ATX_CS0_ADDR, 0x1000);
138 uart_base = (unsigned long) ioremap(0xfd000000UL, 0x1000);
139 rtc_base = ioremap(0xfc000000UL, 0x8000);
140 // ioremap(0xfe000000, 32 << 20);
141 write_c0_wired(0);
142 local_flush_tlb_all();
143 ja_setup_console();
144
145 return 0;
146}
147arch_initcall(per_cpu_mappings);
148
149unsigned long m48t37y_get_time(void)
150{
151 unsigned int year, month, day, hour, min, sec;
152 unsigned long flags;
153
154 spin_lock_irqsave(&rtc_lock, flags);
155 /* stop the update */
156 rtc_base[0x7ff8] = 0x40;
157
158 year = BCD2BIN(rtc_base[0x7fff]);
159 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
160
161 month = BCD2BIN(rtc_base[0x7ffe]);
162
163 day = BCD2BIN(rtc_base[0x7ffd]);
164
165 hour = BCD2BIN(rtc_base[0x7ffb]);
166 min = BCD2BIN(rtc_base[0x7ffa]);
167 sec = BCD2BIN(rtc_base[0x7ff9]);
168
169 /* start the update */
170 rtc_base[0x7ff8] = 0x00;
171 spin_unlock_irqrestore(&rtc_lock, flags);
172
173 return mktime(year, month, day, hour, min, sec);
174}
175
176int m48t37y_set_time(unsigned long sec)
177{
178 struct rtc_time tm;
179 unsigned long flags;
180
181 /* convert to a more useful format -- note months count from 0 */
182 to_tm(sec, &tm);
183 tm.tm_mon += 1;
184
185 spin_lock_irqsave(&rtc_lock, flags);
186 /* enable writing */
187 rtc_base[0x7ff8] = 0x80;
188
189 /* year */
190 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
191 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
192
193 /* month */
194 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
195
196 /* day */
197 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
198
199 /* hour/min/sec */
200 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
201 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
202 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
203
204 /* day of week -- not really used, but let's keep it up-to-date */
205 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
206
207 /* disable writing */
208 rtc_base[0x7ff8] = 0x00;
209 spin_unlock_irqrestore(&rtc_lock, flags);
210
211 return 0;
212}
213
214void __init plat_timer_setup(struct irqaction *irq)
215{
216 setup_irq(8, irq);
217}
218
219/*
220 * Ugly but the least of all evils. TLB initialization did flush the TLB so
221 * We need to setup mappings again before we can touch the RTC.
222 */
223void momenco_time_init(void)
224{
225 wire_stupidity_into_tlb();
226
227 mips_hpt_frequency = cpu_clock / 2;
228
229 rtc_mips_get_time = m48t37y_get_time;
230 rtc_mips_set_time = m48t37y_set_time;
231}
232
233static struct resource mv_pci_io_mem0_resource = {
234 .name = "MV64340 PCI0 IO MEM",
235 .flags = IORESOURCE_IO
236};
237
238static struct resource mv_pci_mem0_resource = {
239 .name = "MV64340 PCI0 MEM",
240 .flags = IORESOURCE_MEM
241};
242
243static struct mv_pci_controller mv_bus0_controller = {
244 .pcic = {
245 .pci_ops = &mv_pci_ops,
246 .mem_resource = &mv_pci_mem0_resource,
247 .io_resource = &mv_pci_io_mem0_resource,
248 },
249 .config_addr = MV64340_PCI_0_CONFIG_ADDR,
250 .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
251};
252
253static uint32_t mv_io_base, mv_io_size;
254
255static void ja_pci0_init(void)
256{
257 uint32_t mem0_base, mem0_size;
258 uint32_t io_base, io_size;
259
260 io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
261 io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
262 mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
263 mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
264
265 mv_pci_io_mem0_resource.start = 0;
266 mv_pci_io_mem0_resource.end = io_size - 1;
267 mv_pci_mem0_resource.start = mem0_base;
268 mv_pci_mem0_resource.end = mem0_base + mem0_size - 1;
269 mv_bus0_controller.pcic.mem_offset = mem0_base;
270 mv_bus0_controller.pcic.io_offset = 0;
271
272 ioport_resource.end = io_size - 1;
273
274 register_pci_controller(&mv_bus0_controller.pcic);
275
276 mv_io_base = io_base;
277 mv_io_size = io_size;
278}
279
280static struct resource mv_pci_io_mem1_resource = {
281 .name = "MV64340 PCI1 IO MEM",
282 .flags = IORESOURCE_IO
283};
284
285static struct resource mv_pci_mem1_resource = {
286 .name = "MV64340 PCI1 MEM",
287 .flags = IORESOURCE_MEM
288};
289
290static struct mv_pci_controller mv_bus1_controller = {
291 .pcic = {
292 .pci_ops = &mv_pci_ops,
293 .mem_resource = &mv_pci_mem1_resource,
294 .io_resource = &mv_pci_io_mem1_resource,
295 },
296 .config_addr = MV64340_PCI_1_CONFIG_ADDR,
297 .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
298};
299
300static __init void ja_pci1_init(void)
301{
302 uint32_t mem0_base, mem0_size;
303 uint32_t io_base, io_size;
304
305 io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
306 io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
307 mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
308 mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
309
310 /*
311 * Here we assume the I/O window of second bus to be contiguous with
312 * the first. A gap is no problem but would waste address space for
313 * remapping the port space.
314 */
315 mv_pci_io_mem1_resource.start = mv_io_size;
316 mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
317 mv_pci_mem1_resource.start = mem0_base;
318 mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
319 mv_bus1_controller.pcic.mem_offset = mem0_base;
320 mv_bus1_controller.pcic.io_offset = 0;
321
322 ioport_resource.end = io_base + io_size -mv_io_base - 1;
323
324 register_pci_controller(&mv_bus1_controller.pcic);
325
326 mv_io_size = io_base + io_size - mv_io_base;
327}
328
329static __init int __init ja_pci_init(void)
330{
331 unsigned long io_v_base;
332 uint32_t enable;
333
334 enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
335
336 /*
337 * We require at least one enabled I/O or PCI memory window or we
338 * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
339 */
340 if (enable & (0x01 << 9) || enable & (0x01 << 10))
341 ja_pci0_init();
342
343 if (enable & (0x01 << 14) || enable & (0x01 << 15))
344 ja_pci1_init();
345
346 if (mv_io_size) {
347 io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size);
348 if (!io_v_base)
349 panic("Could not ioremap I/O port range");
350
351 set_io_port_base(io_v_base);
352 }
353
354 return 0;
355}
356
357arch_initcall(ja_pci_init);
358
359void __init plat_mem_setup(void)
360{
361 unsigned int tmpword;
362
363 board_time_init = momenco_time_init;
364
365 _machine_restart = momenco_jaguar_restart;
366 _machine_halt = momenco_jaguar_halt;
367 pm_power_off = momenco_jaguar_power_off;
368
369 /*
370 * initrd_start = (unsigned long)jaguar_initrd_start;
371 * initrd_end = (unsigned long)jaguar_initrd_start + (ulong)jaguar_initrd_size;
372 * initrd_below_start_ok = 1;
373 */
374
375 wire_stupidity_into_tlb();
376
377 /*
378 * shut down ethernet ports, just to be sure our memory doesn't get
379 * corrupted by random ethernet traffic.
380 */
381 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
382 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
383 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
384 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
385 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
386 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
387 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
388 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
389 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
390 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
391 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
392 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
393 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
394 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
395 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
396 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
397 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2),
398 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
399
400 /* Turn off the Bit-Error LED */
401 JAGUAR_FPGA_WRITE(0x80, CLR);
402
403 tmpword = JAGUAR_FPGA_READ(BOARDREV);
404 if (tmpword < 26)
405 printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n",
406 'A'+tmpword);
407 else
408 printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n",
409 tmpword);
410
411 tmpword = JAGUAR_FPGA_READ(FPGA_REV);
412 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
413 tmpword = JAGUAR_FPGA_READ(RESET_STATUS);
414 printk("Reset reason: 0x%x\n", tmpword);
415 switch (tmpword) {
416 case 0x1:
417 printk(" - Power-up reset\n");
418 break;
419 case 0x2:
420 printk(" - Push-button reset\n");
421 break;
422 case 0x8:
423 printk(" - Watchdog reset\n");
424 break;
425 case 0x10:
426 printk(" - JTAG reset\n");
427 break;
428 default:
429 printk(" - Unknown reset cause\n");
430 }
431 reset_reason = tmpword;
432 JAGUAR_FPGA_WRITE(0xff, RESET_STATUS);
433
434 tmpword = JAGUAR_FPGA_READ(BOARD_STATUS);
435 printk("Board Status register: 0x%02x\n", tmpword);
436 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
437 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
438
439 /* 256MiB of RM9000x2 DDR */
440// add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
441
442 /* 128MiB of MV-64340 DDR */
443// add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
444
445 /* XXX Memory configuration should be picked up from PMON2k */
446#ifdef CONFIG_JAGUAR_DMALOW
447 printk("Jaguar ATX DMA-low mode set\n");
448 add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM);
449 add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM);
450#else
451 /* 128MiB of MV-64340 DDR RAM */
452 printk("Jaguar ATX DMA-low mode is not set\n");
453 add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
454#endif
455
456#ifdef GEMDEBUG_TRACEBUFFER
457 {
458 unsigned int tbControl;
459 tbControl =
460 0 << 26 | /* post trigger delay 0 */
461 0x2 << 16 | /* sequential trace mode */
462 // 0x0 << 16 | /* non-sequential trace mode */
463 // 0xf << 4 | /* watchpoints disabled */
464 2 << 2 | /* armed */
465 2 ; /* interrupt disabled */
466 printk ("setting tbControl = %08lx\n", tbControl);
467 write_32bit_cp0_set1_register($22, tbControl);
468 __asm__ __volatile__(".set noreorder\n\t" \
469 "nop; nop; nop; nop; nop; nop;\n\t" \
470 "nop; nop; nop; nop; nop; nop;\n\t" \
471 ".set reorder\n\t");
472
473 }
474#endif
475}
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