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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/momentum
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/mips/momentum')
-rw-r--r--arch/mips/momentum/jaguar_atx/Makefile12
-rw-r--r--arch/mips/momentum/jaguar_atx/dbg_io.c126
-rw-r--r--arch/mips/momentum/jaguar_atx/int-handler.S128
-rw-r--r--arch/mips/momentum/jaguar_atx/irq.c67
-rw-r--r--arch/mips/momentum/jaguar_atx/ja-console.c106
-rw-r--r--arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h52
-rw-r--r--arch/mips/momentum/jaguar_atx/prom.c266
-rw-r--r--arch/mips/momentum/jaguar_atx/reset.c57
-rw-r--r--arch/mips/momentum/jaguar_atx/setup.c474
-rw-r--r--arch/mips/momentum/ocelot_3/Makefile8
-rw-r--r--arch/mips/momentum/ocelot_3/int-handler.S137
-rw-r--r--arch/mips/momentum/ocelot_3/irq.c81
-rw-r--r--arch/mips/momentum/ocelot_3/ocelot_3_fpga.h57
-rw-r--r--arch/mips/momentum/ocelot_3/prom.c248
-rw-r--r--arch/mips/momentum/ocelot_3/reset.c59
-rw-r--r--arch/mips/momentum/ocelot_3/setup.c398
-rw-r--r--arch/mips/momentum/ocelot_c/Makefile8
-rw-r--r--arch/mips/momentum/ocelot_c/cpci-irq.c153
-rw-r--r--arch/mips/momentum/ocelot_c/dbg_io.c126
-rw-r--r--arch/mips/momentum/ocelot_c/int-handler.S102
-rw-r--r--arch/mips/momentum/ocelot_c/irq.c83
-rw-r--r--arch/mips/momentum/ocelot_c/ocelot_c_fpga.h60
-rw-r--r--arch/mips/momentum/ocelot_c/prom.c243
-rw-r--r--arch/mips/momentum/ocelot_c/reset.c59
-rw-r--r--arch/mips/momentum/ocelot_c/setup.c363
-rw-r--r--arch/mips/momentum/ocelot_c/uart-irq.c147
-rw-r--r--arch/mips/momentum/ocelot_g/Makefile8
-rw-r--r--arch/mips/momentum/ocelot_g/dbg_io.c126
-rw-r--r--arch/mips/momentum/ocelot_g/gt-irq.c214
-rw-r--r--arch/mips/momentum/ocelot_g/int-handler.S131
-rw-r--r--arch/mips/momentum/ocelot_g/irq.c69
-rw-r--r--arch/mips/momentum/ocelot_g/ocelot_pld.h30
-rw-r--r--arch/mips/momentum/ocelot_g/prom.c86
-rw-r--r--arch/mips/momentum/ocelot_g/reset.c47
-rw-r--r--arch/mips/momentum/ocelot_g/setup.c266
35 files changed, 4597 insertions, 0 deletions
diff --git a/arch/mips/momentum/jaguar_atx/Makefile b/arch/mips/momentum/jaguar_atx/Makefile
new file mode 100644
index 000000000000..20bbd3ea44a8
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/Makefile
@@ -0,0 +1,12 @@
1#
2# Makefile for Momentum Computer's Jaguar-ATX board.
3#
4# Note! Dependencies are done automagically by 'make dep', which also
5# removes any old dependencies. DON'T put your own dependencies here
6# unless it's something special (ie not a .c file).
7#
8
9obj-y += int-handler.o irq.o prom.o reset.o setup.o
10
11obj-$(CONFIG_SERIAL_8250_CONSOLE) += ja-console.o
12obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
diff --git a/arch/mips/momentum/jaguar_atx/dbg_io.c b/arch/mips/momentum/jaguar_atx/dbg_io.c
new file mode 100644
index 000000000000..542eac82b63c
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/dbg_io.c
@@ -0,0 +1,126 @@
1#include <linux/config.h>
2
3#if defined(CONFIG_REMOTE_DEBUG)
4
5#include <asm/serial.h> /* For the serial port location and base baud */
6
7/* --- CONFIG --- */
8
9typedef unsigned char uint8;
10typedef unsigned int uint32;
11
12/* --- END OF CONFIG --- */
13
14#define UART16550_BAUD_2400 2400
15#define UART16550_BAUD_4800 4800
16#define UART16550_BAUD_9600 9600
17#define UART16550_BAUD_19200 19200
18#define UART16550_BAUD_38400 38400
19#define UART16550_BAUD_57600 57600
20#define UART16550_BAUD_115200 115200
21
22#define UART16550_PARITY_NONE 0
23#define UART16550_PARITY_ODD 0x08
24#define UART16550_PARITY_EVEN 0x18
25#define UART16550_PARITY_MARK 0x28
26#define UART16550_PARITY_SPACE 0x38
27
28#define UART16550_DATA_5BIT 0x0
29#define UART16550_DATA_6BIT 0x1
30#define UART16550_DATA_7BIT 0x2
31#define UART16550_DATA_8BIT 0x3
32
33#define UART16550_STOP_1BIT 0x0
34#define UART16550_STOP_2BIT 0x4
35
36/* ----------------------------------------------------- */
37
38/* === CONFIG === */
39
40/* [jsun] we use the second serial port for kdb */
41#define BASE OCELOT_SERIAL1_BASE
42#define MAX_BAUD OCELOT_BASE_BAUD
43
44/* === END OF CONFIG === */
45
46#define REG_OFFSET 4
47
48/* register offset */
49#define OFS_RCV_BUFFER 0
50#define OFS_TRANS_HOLD 0
51#define OFS_SEND_BUFFER 0
52#define OFS_INTR_ENABLE (1*REG_OFFSET)
53#define OFS_INTR_ID (2*REG_OFFSET)
54#define OFS_DATA_FORMAT (3*REG_OFFSET)
55#define OFS_LINE_CONTROL (3*REG_OFFSET)
56#define OFS_MODEM_CONTROL (4*REG_OFFSET)
57#define OFS_RS232_OUTPUT (4*REG_OFFSET)
58#define OFS_LINE_STATUS (5*REG_OFFSET)
59#define OFS_MODEM_STATUS (6*REG_OFFSET)
60#define OFS_RS232_INPUT (6*REG_OFFSET)
61#define OFS_SCRATCH_PAD (7*REG_OFFSET)
62
63#define OFS_DIVISOR_LSB (0*REG_OFFSET)
64#define OFS_DIVISOR_MSB (1*REG_OFFSET)
65
66
67/* memory-mapped read/write of the port */
68#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
69#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
70
71void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
72{
73 /* disable interrupts */
74 UART16550_WRITE(OFS_INTR_ENABLE, 0);
75
76 /* set up buad rate */
77 {
78 uint32 divisor;
79
80 /* set DIAB bit */
81 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
82
83 /* set divisor */
84 divisor = MAX_BAUD / baud;
85 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
86 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
87
88 /* clear DIAB bit */
89 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
90 }
91
92 /* set data format */
93 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
94}
95
96static int remoteDebugInitialized = 0;
97
98uint8 getDebugChar(void)
99{
100 if (!remoteDebugInitialized) {
101 remoteDebugInitialized = 1;
102 debugInit(UART16550_BAUD_38400,
103 UART16550_DATA_8BIT,
104 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
105 }
106
107 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
108 return UART16550_READ(OFS_RCV_BUFFER);
109}
110
111
112int putDebugChar(uint8 byte)
113{
114 if (!remoteDebugInitialized) {
115 remoteDebugInitialized = 1;
116 debugInit(UART16550_BAUD_38400,
117 UART16550_DATA_8BIT,
118 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
119 }
120
121 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
122 UART16550_WRITE(OFS_SEND_BUFFER, byte);
123 return 1;
124}
125
126#endif
diff --git a/arch/mips/momentum/jaguar_atx/int-handler.S b/arch/mips/momentum/jaguar_atx/int-handler.S
new file mode 100644
index 000000000000..43fd5a58077c
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/int-handler.S
@@ -0,0 +1,128 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on work:
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: jsun@mvista.com or jsun@junsun.net
8 *
9 * First-level interrupt dispatcher for Jaguar-ATX board.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <asm/asm.h>
17#include <asm/mipsregs.h>
18#include <asm/addrspace.h>
19#include <asm/regdef.h>
20#include <asm/stackframe.h>
21
22/*
23 * First level interrupt dispatcher for Ocelot-CS board
24 */
25 .align 5
26 NESTED(jaguar_handle_int, PT_SIZE, sp)
27 SAVE_ALL
28 CLI
29 .set at
30 mfc0 t0, CP0_CAUSE
31 mfc0 t2, CP0_STATUS
32
33 and t0, t2
34
35 andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */
36 bnez t1, ll_sw0_irq
37 andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */
38 bnez t1, ll_sw1_irq
39 andi t1, t0, STATUSF_IP2 /* int0 hardware line */
40 bnez t1, ll_pcixa_irq
41 andi t1, t0, STATUSF_IP3 /* int1 hardware line */
42 bnez t1, ll_pcixb_irq
43 andi t1, t0, STATUSF_IP4 /* int2 hardware line */
44 bnez t1, ll_pcia_irq
45 andi t1, t0, STATUSF_IP5 /* int3 hardware line */
46 bnez t1, ll_pcib_irq
47 andi t1, t0, STATUSF_IP6 /* int4 hardware line */
48 bnez t1, ll_uart_irq
49 andi t1, t0, STATUSF_IP7 /* cpu timer */
50 bnez t1, ll_cputimer_irq
51
52 nop
53 nop
54
55 /* now look at extended interrupts */
56 mfc0 t0, CP0_CAUSE
57 cfc0 t1, CP0_S1_INTCONTROL
58
59 /* shift the mask 8 bits left to line up the bits */
60 sll t2, t1, 8
61
62 and t0, t2
63 srl t0, t0, 16
64
65 andi t1, t0, STATUSF_IP8 /* int6 hardware line */
66 bnez t1, ll_mv64340_decode_irq
67
68 nop
69 nop
70
71 .set reorder
72
73 /* wrong alarm or masked ... */
74 j spurious_interrupt
75 nop
76 END(jaguar_handle_int)
77
78 .align 5
79ll_sw0_irq:
80 li a0, 0
81 move a1, sp
82 jal do_IRQ
83 j ret_from_irq
84ll_sw1_irq:
85 li a0, 1
86 move a1, sp
87 jal do_IRQ
88 j ret_from_irq
89ll_pcixa_irq:
90 li a0, 2
91 move a1, sp
92 jal do_IRQ
93 j ret_from_irq
94
95ll_pcixb_irq:
96 li a0, 3
97 move a1, sp
98 jal do_IRQ
99 j ret_from_irq
100
101ll_pcia_irq:
102 li a0, 4
103 move a1, sp
104 jal do_IRQ
105 j ret_from_irq
106
107ll_pcib_irq:
108 li a0, 5
109 move a1, sp
110 jal do_IRQ
111 j ret_from_irq
112
113ll_uart_irq:
114 li a0, 6
115 move a1, sp
116 jal do_IRQ
117 j ret_from_irq
118
119ll_cputimer_irq:
120 li a0, 7
121 move a1, sp
122 jal ll_timer_interrupt
123 j ret_from_irq
124
125ll_mv64340_decode_irq:
126 move a0, sp
127 jal ll_mv64340_irq
128 j ret_from_irq
diff --git a/arch/mips/momentum/jaguar_atx/irq.c b/arch/mips/momentum/jaguar_atx/irq.c
new file mode 100644
index 000000000000..15588f91ace2
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/irq.c
@@ -0,0 +1,67 @@
1/*
2 * Copyright (C) 2002 Momentum Computer, Inc.
3 * Author: Matthew Dharm, mdharm@momenco.com
4 *
5 * Based on work by:
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Author: RidgeRun, Inc.
8 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
9 *
10 * Copyright 2001 MontaVista Software Inc.
11 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
12 *
13 * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35#include <linux/init.h>
36#include <linux/interrupt.h>
37#include <linux/signal.h>
38#include <linux/types.h>
39#include <asm/irq_cpu.h>
40#include <asm/mipsregs.h>
41
42extern asmlinkage void jaguar_handle_int(void);
43
44static struct irqaction cascade_mv64340 = {
45 no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
46};
47
48void __init arch_init_irq(void)
49{
50 /*
51 * Clear all of the interrupts while we change the able around a bit.
52 * int-handler is not on bootstrap
53 */
54 clear_c0_status(ST0_IM);
55
56 /* Sets the first-level interrupt dispatcher. */
57 set_except_vector(0, jaguar_handle_int);
58 mips_cpu_irq_init(0);
59 rm7k_cpu_irq_init(8);
60
61 /* set up the cascading interrupts */
62 setup_irq(8, &cascade_mv64340);
63
64 mv64340_irq_init(16);
65
66 set_c0_status(ST0_IM);
67}
diff --git a/arch/mips/momentum/jaguar_atx/ja-console.c b/arch/mips/momentum/jaguar_atx/ja-console.c
new file mode 100644
index 000000000000..da6e1ed34db1
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/ja-console.c
@@ -0,0 +1,106 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2001, 2002, 2004 Ralf Baechle
7 */
8#include <linux/init.h>
9#include <linux/console.h>
10#include <linux/kdev_t.h>
11#include <linux/major.h>
12#include <linux/termios.h>
13#include <linux/sched.h>
14#include <linux/tty.h>
15
16#include <linux/serial.h>
17#include <linux/serial_core.h>
18#include <asm/serial.h>
19
20/* SUPERIO uart register map */
21struct ja_uartregs {
22 union {
23 volatile u8 pad0[3];
24 volatile u8 rbr; /* read only, DLAB == 0 */
25 volatile u8 pad1[3];
26 volatile u8 thr; /* write only, DLAB == 0 */
27 volatile u8 pad2[3];
28 volatile u8 dll; /* DLAB == 1 */
29 } u1;
30 union {
31 volatile u8 pad0[3];
32 volatile u8 ier; /* DLAB == 0 */
33 volatile u8 pad1[3];
34 volatile u8 dlm; /* DLAB == 1 */
35 } u2;
36 union {
37 volatile u8 pad0[3];
38 volatile u8 iir; /* read only */
39 volatile u8 pad1[3];
40 volatile u8 fcr; /* write only */
41 } u3;
42 volatile u8 pad0[3];
43 volatile u8 iu_lcr;
44 volatile u8 pad1[3];
45 volatile u8 iu_mcr;
46 volatile u8 pad2[3];
47 volatile u8 iu_lsr;
48 volatile u8 pad3[3];
49 volatile u8 iu_msr;
50 volatile u8 pad4[3];
51 volatile u8 iu_scr;
52} ja_uregs_t;
53
54#define iu_rbr u1.rbr
55#define iu_thr u1.thr
56#define iu_dll u1.dll
57#define iu_ier u2.ier
58#define iu_dlm u2.dlm
59#define iu_iir u3.iir
60#define iu_fcr u3.fcr
61
62extern unsigned long uart_base;
63
64static inline struct ja_uartregs *console_uart(void)
65{
66 return (struct ja_uartregs *) (uart_base + 0x23UL);
67}
68
69void prom_putchar(char c)
70{
71 struct ja_uartregs *uart = console_uart();
72
73 while ((uart->iu_lsr & 0x20) == 0);
74 uart->iu_thr = c;
75}
76
77char __init prom_getchar(void)
78{
79 return 0;
80}
81
82static void inline ja_console_probe(void)
83{
84 struct uart_port up;
85
86 /*
87 * Register to interrupt zero because we share the interrupt with
88 * the serial driver which we don't properly support yet.
89 */
90 memset(&up, 0, sizeof(up));
91 up.membase = (unsigned char *) uart_base + 0x23UL;
92 up.irq = JAGUAR_ATX_SERIAL1_IRQ;
93 up.uartclk = JAGUAR_ATX_UART_CLK;
94 up.regshift = 2;
95 up.iotype = UPIO_MEM;
96 up.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
97 up.line = 0;
98
99 if (early_serial_setup(&up))
100 printk(KERN_ERR "Early serial init of port 0 failed\n");
101}
102
103__init void ja_setup_console(void)
104{
105 ja_console_probe();
106}
diff --git a/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h b/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h
new file mode 100644
index 000000000000..6978654c712b
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h
@@ -0,0 +1,52 @@
1/*
2 * Jaguar-ATX Board Register Definitions
3 *
4 * (C) 2002 Momentum Computer Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#ifndef __JAGUAR_ATX_FPGA_H__
27#define __JAGUAR_ATX_FPGA_H__
28
29#define JAGUAR_ATX_REG_BOARDREV 0x0
30#define JAGUAR_ATX_REG_FPGA_REV 0x1
31#define JAGUAR_ATX_REG_FPGA_TYPE 0x2
32#define JAGUAR_ATX_REG_RESET_STATUS 0x3
33#define JAGUAR_ATX_REG_BOARD_STATUS 0x4
34#define JAGUAR_ATX_REG_RESERVED1 0x5
35#define JAGUAR_ATX_REG_SET 0x6
36#define JAGUAR_ATX_REG_CLR 0x7
37#define JAGUAR_ATX_REG_EEPROM_MODE 0x9
38#define JAGUAR_ATX_REG_RESERVED2 0xa
39#define JAGUAR_ATX_REG_RESERVED3 0xb
40#define JAGUAR_ATX_REG_RESERVED4 0xc
41#define JAGUAR_ATX_REG_PHY_INTSTAT 0xd
42#define JAGUAR_ATX_REG_RESERVED5 0xe
43#define JAGUAR_ATX_REG_RESERVED6 0xf
44
45#define JAGUAR_ATX_CS0_ADDR 0xfc000000L
46
47extern unsigned long ja_fpga_base;
48
49#define JAGUAR_FPGA_WRITE(x,y) writeb(x, ja_fpga_base + JAGUAR_ATX_REG_##y)
50#define JAGUAR_FPGA_READ(x) readb(ja_fpga_base + JAGUAR_ATX_REG_##x)
51
52#endif
diff --git a/arch/mips/momentum/jaguar_atx/prom.c b/arch/mips/momentum/jaguar_atx/prom.c
new file mode 100644
index 000000000000..fa5982ac0ac6
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/prom.c
@@ -0,0 +1,266 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Louis Hamilton, Red Hat, Inc.
6 * hamilton@redhat.com [MIPS64 modifications]
7 *
8 * Based on Ocelot Linux port, which is
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: jsun@mvista.com or jsun@junsun.net
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * Added changes for SMP - Manish Lachwani (lachwani@pmc-sierra.com)
18 */
19#include <linux/config.h>
20#include <linux/init.h>
21#include <linux/mm.h>
22#include <linux/sched.h>
23#include <linux/bootmem.h>
24
25#include <asm/addrspace.h>
26#include <asm/bootinfo.h>
27#include <asm/mv64340.h>
28#include <asm/pmon.h>
29
30#include "jaguar_atx_fpga.h"
31
32extern void ja_setup_console(void);
33
34struct callvectors *debug_vectors;
35
36extern unsigned long cpu_clock;
37
38const char *get_system_type(void)
39{
40 return "Momentum Jaguar-ATX";
41}
42
43#ifdef CONFIG_MV643XX_ETH
44extern unsigned char prom_mac_addr_base[6];
45
46static void burn_clocks(void)
47{
48 int i;
49
50 /* this loop should burn at least 1us -- this should be plenty */
51 for (i = 0; i < 0x10000; i++)
52 ;
53}
54
55static u8 exchange_bit(u8 val, u8 cs)
56{
57 /* place the data */
58 JAGUAR_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
59 burn_clocks();
60
61 /* turn the clock on */
62 JAGUAR_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
63 burn_clocks();
64
65 /* turn the clock off and read-strobe */
66 JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
67
68 /* return the data */
69 return ((JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
70}
71
72void get_mac(char dest[6])
73{
74 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
75 int i,j;
76
77 for (i = 0; i < 12; i++)
78 exchange_bit(read_opcode[i], 1);
79
80 for (j = 0; j < 6; j++) {
81 dest[j] = 0;
82 for (i = 0; i < 8; i++) {
83 dest[j] <<= 1;
84 dest[j] |= exchange_bit(0, 1);
85 }
86 }
87
88 /* turn off CS */
89 exchange_bit(0,0);
90}
91#endif
92
93#ifdef CONFIG_MIPS64
94
95unsigned long signext(unsigned long addr)
96{
97 addr &= 0xffffffff;
98 return (unsigned long)((int)addr);
99}
100
101void *get_arg(unsigned long args, int arc)
102{
103 unsigned long ul;
104 unsigned char *puc, uc;
105
106 args += (arc * 4);
107 ul = (unsigned long)signext(args);
108 puc = (unsigned char *)ul;
109 if (puc == 0)
110 return (void *)0;
111
112#ifdef CONFIG_CPU_LITTLE_ENDIAN
113 uc = *puc++;
114 l = (unsigned long)uc;
115 uc = *puc++;
116 ul |= (((unsigned long)uc) << 8);
117 uc = *puc++;
118 ul |= (((unsigned long)uc) << 16);
119 uc = *puc++;
120 ul |= (((unsigned long)uc) << 24);
121#else
122 uc = *puc++;
123 ul = ((unsigned long)uc) << 24;
124 uc = *puc++;
125 ul |= (((unsigned long)uc) << 16);
126 uc = *puc++;
127 ul |= (((unsigned long)uc) << 8);
128 uc = *puc++;
129 ul |= ((unsigned long)uc);
130#endif
131 ul = signext(ul);
132
133 return (void *)ul;
134}
135
136char *arg64(unsigned long addrin, int arg_index)
137{
138 unsigned long args;
139 char *p;
140
141 args = signext(addrin);
142 p = (char *)get_arg(args, arg_index);
143
144 return p;
145}
146#endif /* CONFIG_MIPS64 */
147
148/* PMON passes arguments in C main() style */
149void __init prom_init(void)
150{
151 int argc = fw_arg0;
152 char **arg = (char **) fw_arg1;
153 char **env = (char **) fw_arg2;
154 struct callvectors *cv = (struct callvectors *) fw_arg3;
155 int i;
156
157#ifdef CONFIG_SERIAL_8250_CONSOLE
158// ja_setup_console(); /* The very first thing. */
159#endif
160
161#ifdef CONFIG_MIPS64
162 char *ptr;
163
164 printk("Mips64 Jaguar-ATX\n");
165 /* save the PROM vectors for debugging use */
166 debug_vectors = (struct callvectors *)signext((unsigned long)cv);
167
168 /* arg[0] is "g", the rest is boot parameters */
169 arcs_cmdline[0] = '\0';
170
171 for (i = 1; i < argc; i++) {
172 ptr = (char *)arg64((unsigned long)arg, i);
173 if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
174 sizeof(arcs_cmdline))
175 break;
176 strcat(arcs_cmdline, ptr);
177 strcat(arcs_cmdline, " ");
178 }
179
180 i = 0;
181 while (1) {
182 ptr = (char *)arg64((unsigned long)env, i);
183 if (! ptr)
184 break;
185
186 if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
187 marvell_base = simple_strtol(ptr + strlen("gtbase="),
188 NULL, 16);
189
190 if ((marvell_base & 0xffffffff00000000) == 0)
191 marvell_base |= 0xffffffff00000000;
192
193 printk("marvell_base set to 0x%016lx\n", marvell_base);
194 }
195 if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
196 cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
197 NULL, 10);
198 printk("cpu_clock set to %d\n", cpu_clock);
199 }
200 i++;
201 }
202 printk("arcs_cmdline: %s\n", arcs_cmdline);
203
204#else /* CONFIG_MIPS64 */
205 /* save the PROM vectors for debugging use */
206 debug_vectors = cv;
207
208 /* arg[0] is "g", the rest is boot parameters */
209 arcs_cmdline[0] = '\0';
210 for (i = 1; i < argc; i++) {
211 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
212 >= sizeof(arcs_cmdline))
213 break;
214 strcat(arcs_cmdline, arg[i]);
215 strcat(arcs_cmdline, " ");
216 }
217
218 while (*env) {
219 if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
220 marvell_base = simple_strtol(*env + strlen("gtbase="),
221 NULL, 16);
222 }
223 if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
224 cpu_clock = simple_strtol(*env + strlen("cpuclock="),
225 NULL, 10);
226 }
227 env++;
228 }
229#endif /* CONFIG_MIPS64 */
230 mips_machgroup = MACH_GROUP_MOMENCO;
231 mips_machtype = MACH_MOMENCO_JAGUAR_ATX;
232
233#ifdef CONFIG_MV643XX_ETH
234 /* get the base MAC address for on-board ethernet ports */
235 get_mac(prom_mac_addr_base);
236#endif
237}
238
239void __init prom_free_prom_memory(void)
240{
241}
242
243void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
244{
245}
246
247int prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp)
248{
249 /* Clear the semaphore */
250 *(volatile uint32_t *)(0xbb000a68) = 0x80000000;
251
252 return 1;
253}
254
255void prom_init_secondary(void)
256{
257 clear_c0_config(CONF_CM_CMASK);
258 set_c0_config(0x2);
259
260 clear_c0_status(ST0_IM);
261 set_c0_status(0x1ffff);
262}
263
264void prom_smp_finish(void)
265{
266}
diff --git a/arch/mips/momentum/jaguar_atx/reset.c b/arch/mips/momentum/jaguar_atx/reset.c
new file mode 100644
index 000000000000..48039484cdf9
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/reset.c
@@ -0,0 +1,57 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 * Copyright (C) 2002 Momentum Computer Inc.
12 * Author: Matthew Dharm <mdharm@momenco.com>
13 *
14 * Louis Hamilton, Red Hat, Inc.
15 * hamilton@redhat.com [MIPS64 modifications]
16 */
17#include <linux/config.h>
18#include <linux/sched.h>
19#include <linux/mm.h>
20#include <asm/io.h>
21#include <asm/pgtable.h>
22#include <asm/processor.h>
23#include <asm/reboot.h>
24#include <asm/system.h>
25#include <linux/delay.h>
26
27void momenco_jaguar_restart(char *command)
28{
29 /* base address of timekeeper portion of part */
30#ifdef CONFIG_MIPS64
31 void *nvram = (void*) 0xfffffffffc807000;
32#else
33 void *nvram = (void*) 0xfc807000;
34#endif
35 /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
36 writeb(0x84, nvram + 0xff7);
37
38 /* wait for the watchdog to go off */
39 mdelay(100+(1000/16));
40
41 /* if the watchdog fails for some reason, let people know */
42 printk(KERN_NOTICE "Watchdog reset failed\n");
43}
44
45void momenco_jaguar_halt(void)
46{
47 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
48 while (1)
49 __asm__(".set\tmips3\n\t"
50 "wait\n\t"
51 ".set\tmips0");
52}
53
54void momenco_jaguar_power_off(void)
55{
56 momenco_jaguar_halt();
57}
diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c
new file mode 100644
index 000000000000..30462e715066
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/setup.c
@@ -0,0 +1,474 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Jaguar-ATX board dependent boot routines
4 *
5 * Copyright (C) 1996, 1997, 2001, 2004 Ralf Baechle (ralf@linux-mips.org)
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
9 *
10 * Author: Matthew Dharm, Momentum Computer
11 * mdharm@momenco.com
12 *
13 * Louis Hamilton, Red Hat, Inc.
14 * hamilton@redhat.com [MIPS64 modifications]
15 *
16 * Author: RidgeRun, Inc.
17 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
18 *
19 * Copyright 2001 MontaVista Software Inc.
20 * Author: jsun@mvista.com or jsun@junsun.net
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License as published by the
24 * Free Software Foundation; either version 2 of the License, or (at your
25 * option) any later version.
26 *
27 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
30 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
33 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * You should have received a copy of the GNU General Public License along
39 * with this program; if not, write to the Free Software Foundation, Inc.,
40 * 675 Mass Ave, Cambridge, MA 02139, USA.
41 */
42#include <linux/config.h>
43#include <linux/bcd.h>
44#include <linux/init.h>
45#include <linux/kernel.h>
46#include <linux/types.h>
47#include <linux/mm.h>
48#include <linux/bootmem.h>
49#include <linux/module.h>
50#include <linux/pci.h>
51#include <linux/swap.h>
52#include <linux/ioport.h>
53#include <linux/sched.h>
54#include <linux/interrupt.h>
55#include <linux/timex.h>
56#include <linux/vmalloc.h>
57#include <asm/time.h>
58#include <asm/bootinfo.h>
59#include <asm/page.h>
60#include <asm/io.h>
61#include <asm/irq.h>
62#include <asm/processor.h>
63#include <asm/ptrace.h>
64#include <asm/reboot.h>
65#include <asm/tlbflush.h>
66#include <asm/mv64340.h>
67
68#include "jaguar_atx_fpga.h"
69
70extern unsigned long mv64340_sram_base;
71unsigned long cpu_clock;
72
73/* These functions are used for rebooting or halting the machine*/
74extern void momenco_jaguar_restart(char *command);
75extern void momenco_jaguar_halt(void);
76extern void momenco_jaguar_power_off(void);
77
78void momenco_time_init(void);
79
80static char reset_reason;
81
82static inline unsigned long ENTRYLO(unsigned long paddr)
83{
84 return ((paddr & PAGE_MASK) |
85 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
86 _CACHE_UNCACHED)) >> 6;
87}
88
89void __init bus_error_init(void) { /* nothing */ }
90
91/*
92 * Load a few TLB entries for the MV64340 and perhiperals. The MV64340 is going
93 * to be hit on every IRQ anyway - there's absolutely no point in letting it be
94 * a random TLB entry, as it'll just cause needless churning of the TLB. And we
95 * use the other half for the serial port, which is just a PITA otherwise :)
96 *
97 * Device Physical Virtual
98 * MV64340 Internal Regs 0xf4000000 0xf4000000
99 * Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
100 * NVRAM (CS1) 0xfc800000 0xfc800000
101 * UARTs (CS2) 0xfd000000 0xfd000000
102 * Internal SRAM 0xfe000000 0xfe000000
103 * M-Systems DOC (CS3) 0xff000000 0xff000000
104 */
105
106static __init void wire_stupidity_into_tlb(void)
107{
108#ifdef CONFIG_MIPS32
109 write_c0_wired(0);
110 local_flush_tlb_all();
111
112 /* marvell and extra space */
113 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
114 0xf4000000UL, PM_64K);
115 /* fpga, rtc, and uart */
116 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000),
117 0xfc000000UL, PM_16M);
118// /* m-sys and internal SRAM */
119// add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000),
120// 0xfe000000UL, PM_16M);
121
122 marvell_base = 0xf4000000;
123 //mv64340_sram_base = 0xfe000000; /* Currently unused */
124#endif
125}
126
127unsigned long marvell_base = 0xf4000000L;
128unsigned long ja_fpga_base = JAGUAR_ATX_CS0_ADDR;
129unsigned long uart_base = 0xfd000000L;
130static unsigned char *rtc_base = (unsigned char*) 0xfc800000L;
131
132EXPORT_SYMBOL(marvell_base);
133
134static __init int per_cpu_mappings(void)
135{
136 marvell_base = (unsigned long) ioremap(0xf4000000, 0x10000);
137 ja_fpga_base = (unsigned long) ioremap(JAGUAR_ATX_CS0_ADDR, 0x1000);
138 uart_base = (unsigned long) ioremap(0xfd000000UL, 0x1000);
139 rtc_base = ioremap(0xfc000000UL, 0x8000);
140 // ioremap(0xfe000000, 32 << 20);
141 write_c0_wired(0);
142 local_flush_tlb_all();
143 ja_setup_console();
144
145 return 0;
146}
147arch_initcall(per_cpu_mappings);
148
149unsigned long m48t37y_get_time(void)
150{
151 unsigned int year, month, day, hour, min, sec;
152
153 /* stop the update */
154 rtc_base[0x7ff8] = 0x40;
155
156 year = BCD2BIN(rtc_base[0x7fff]);
157 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
158
159 month = BCD2BIN(rtc_base[0x7ffe]);
160
161 day = BCD2BIN(rtc_base[0x7ffd]);
162
163 hour = BCD2BIN(rtc_base[0x7ffb]);
164 min = BCD2BIN(rtc_base[0x7ffa]);
165 sec = BCD2BIN(rtc_base[0x7ff9]);
166
167 /* start the update */
168 rtc_base[0x7ff8] = 0x00;
169
170 return mktime(year, month, day, hour, min, sec);
171}
172
173int m48t37y_set_time(unsigned long sec)
174{
175 struct rtc_time tm;
176
177 /* convert to a more useful format -- note months count from 0 */
178 to_tm(sec, &tm);
179 tm.tm_mon += 1;
180
181 /* enable writing */
182 rtc_base[0x7ff8] = 0x80;
183
184 /* year */
185 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
186 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
187
188 /* month */
189 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
190
191 /* day */
192 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
193
194 /* hour/min/sec */
195 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
196 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
197 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
198
199 /* day of week -- not really used, but let's keep it up-to-date */
200 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
201
202 /* disable writing */
203 rtc_base[0x7ff8] = 0x00;
204
205 return 0;
206}
207
208void momenco_timer_setup(struct irqaction *irq)
209{
210 setup_irq(8, irq);
211}
212
213/*
214 * Ugly but the least of all evils. TLB initialization did flush the TLB so
215 * We need to setup mappings again before we can touch the RTC.
216 */
217void momenco_time_init(void)
218{
219 wire_stupidity_into_tlb();
220
221 mips_hpt_frequency = cpu_clock / 2;
222 board_timer_setup = momenco_timer_setup;
223
224 rtc_get_time = m48t37y_get_time;
225 rtc_set_time = m48t37y_set_time;
226}
227
228static struct resource mv_pci_io_mem0_resource = {
229 .name = "MV64340 PCI0 IO MEM",
230 .flags = IORESOURCE_IO
231};
232
233static struct resource mv_pci_mem0_resource = {
234 .name = "MV64340 PCI0 MEM",
235 .flags = IORESOURCE_MEM
236};
237
238static struct mv_pci_controller mv_bus0_controller = {
239 .pcic = {
240 .pci_ops = &mv_pci_ops,
241 .mem_resource = &mv_pci_mem0_resource,
242 .io_resource = &mv_pci_io_mem0_resource,
243 },
244 .config_addr = MV64340_PCI_0_CONFIG_ADDR,
245 .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
246};
247
248static uint32_t mv_io_base, mv_io_size;
249
250static void ja_pci0_init(void)
251{
252 uint32_t mem0_base, mem0_size;
253 uint32_t io_base, io_size;
254
255 io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
256 io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
257 mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
258 mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
259
260 mv_pci_io_mem0_resource.start = 0;
261 mv_pci_io_mem0_resource.end = io_size - 1;
262 mv_pci_mem0_resource.start = mem0_base;
263 mv_pci_mem0_resource.end = mem0_base + mem0_size - 1;
264 mv_bus0_controller.pcic.mem_offset = mem0_base;
265 mv_bus0_controller.pcic.io_offset = 0;
266
267 ioport_resource.end = io_size - 1;
268
269 register_pci_controller(&mv_bus0_controller.pcic);
270
271 mv_io_base = io_base;
272 mv_io_size = io_size;
273}
274
275static struct resource mv_pci_io_mem1_resource = {
276 .name = "MV64340 PCI1 IO MEM",
277 .flags = IORESOURCE_IO
278};
279
280static struct resource mv_pci_mem1_resource = {
281 .name = "MV64340 PCI1 MEM",
282 .flags = IORESOURCE_MEM
283};
284
285static struct mv_pci_controller mv_bus1_controller = {
286 .pcic = {
287 .pci_ops = &mv_pci_ops,
288 .mem_resource = &mv_pci_mem1_resource,
289 .io_resource = &mv_pci_io_mem1_resource,
290 },
291 .config_addr = MV64340_PCI_1_CONFIG_ADDR,
292 .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
293};
294
295static __init void ja_pci1_init(void)
296{
297 uint32_t mem0_base, mem0_size;
298 uint32_t io_base, io_size;
299
300 io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
301 io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
302 mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
303 mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
304
305 /*
306 * Here we assume the I/O window of second bus to be contiguous with
307 * the first. A gap is no problem but would waste address space for
308 * remapping the port space.
309 */
310 mv_pci_io_mem1_resource.start = mv_io_size;
311 mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
312 mv_pci_mem1_resource.start = mem0_base;
313 mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
314 mv_bus1_controller.pcic.mem_offset = mem0_base;
315 mv_bus1_controller.pcic.io_offset = 0;
316
317 ioport_resource.end = io_base + io_size -mv_io_base - 1;
318
319 register_pci_controller(&mv_bus1_controller.pcic);
320
321 mv_io_size = io_base + io_size - mv_io_base;
322}
323
324static __init int __init ja_pci_init(void)
325{
326 unsigned long io_v_base;
327 uint32_t enable;
328
329 enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
330
331 /*
332 * We require at least one enabled I/O or PCI memory window or we
333 * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
334 */
335 if (enable & (0x01 << 9) || enable & (0x01 << 10))
336 ja_pci0_init();
337
338 if (enable & (0x01 << 14) || enable & (0x01 << 15))
339 ja_pci1_init();
340
341 if (mv_io_size) {
342 io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size);
343 if (!io_v_base)
344 panic("Could not ioremap I/O port range");
345
346 set_io_port_base(io_v_base);
347 }
348
349 return 0;
350}
351
352arch_initcall(ja_pci_init);
353
354static int __init momenco_jaguar_atx_setup(void)
355{
356 unsigned int tmpword;
357
358 board_time_init = momenco_time_init;
359
360 _machine_restart = momenco_jaguar_restart;
361 _machine_halt = momenco_jaguar_halt;
362 _machine_power_off = momenco_jaguar_power_off;
363
364 /*
365 * initrd_start = (ulong)jaguar_initrd_start;
366 * initrd_end = (ulong)jaguar_initrd_start + (ulong)jaguar_initrd_size;
367 * initrd_below_start_ok = 1;
368 */
369
370 wire_stupidity_into_tlb();
371
372 /*
373 * shut down ethernet ports, just to be sure our memory doesn't get
374 * corrupted by random ethernet traffic.
375 */
376 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
377 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
378 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
379 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
380 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
381 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
382 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
383 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
384 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
385 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
386 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
387 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
388 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
389 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
390 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
391 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
392 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2),
393 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
394
395 /* Turn off the Bit-Error LED */
396 JAGUAR_FPGA_WRITE(0x80, CLR);
397
398 tmpword = JAGUAR_FPGA_READ(BOARDREV);
399 if (tmpword < 26)
400 printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n",
401 'A'+tmpword);
402 else
403 printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n",
404 tmpword);
405
406 tmpword = JAGUAR_FPGA_READ(FPGA_REV);
407 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
408 tmpword = JAGUAR_FPGA_READ(RESET_STATUS);
409 printk("Reset reason: 0x%x\n", tmpword);
410 switch (tmpword) {
411 case 0x1:
412 printk(" - Power-up reset\n");
413 break;
414 case 0x2:
415 printk(" - Push-button reset\n");
416 break;
417 case 0x8:
418 printk(" - Watchdog reset\n");
419 break;
420 case 0x10:
421 printk(" - JTAG reset\n");
422 break;
423 default:
424 printk(" - Unknown reset cause\n");
425 }
426 reset_reason = tmpword;
427 JAGUAR_FPGA_WRITE(0xff, RESET_STATUS);
428
429 tmpword = JAGUAR_FPGA_READ(BOARD_STATUS);
430 printk("Board Status register: 0x%02x\n", tmpword);
431 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
432 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
433
434 /* 256MiB of RM9000x2 DDR */
435// add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
436
437 /* 128MiB of MV-64340 DDR */
438// add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
439
440 /* XXX Memory configuration should be picked up from PMON2k */
441#ifdef CONFIG_JAGUAR_DMALOW
442 printk("Jaguar ATX DMA-low mode set\n");
443 add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM);
444 add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM);
445#else
446 /* 128MiB of MV-64340 DDR RAM */
447 printk("Jaguar ATX DMA-low mode is not set\n");
448 add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
449#endif
450
451#ifdef GEMDEBUG_TRACEBUFFER
452 {
453 unsigned int tbControl;
454 tbControl =
455 0 << 26 | /* post trigger delay 0 */
456 0x2 << 16 | /* sequential trace mode */
457 // 0x0 << 16 | /* non-sequential trace mode */
458 // 0xf << 4 | /* watchpoints disabled */
459 2 << 2 | /* armed */
460 2 ; /* interrupt disabled */
461 printk ("setting tbControl = %08lx\n", tbControl);
462 write_32bit_cp0_set1_register($22, tbControl);
463 __asm__ __volatile__(".set noreorder\n\t" \
464 "nop; nop; nop; nop; nop; nop;\n\t" \
465 "nop; nop; nop; nop; nop; nop;\n\t" \
466 ".set reorder\n\t");
467
468 }
469#endif
470
471 return 0;
472}
473
474early_initcall(momenco_jaguar_atx_setup);
diff --git a/arch/mips/momentum/ocelot_3/Makefile b/arch/mips/momentum/ocelot_3/Makefile
new file mode 100644
index 000000000000..aab8fd89f830
--- /dev/null
+++ b/arch/mips/momentum/ocelot_3/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for Momentum Computer's Ocelot-3 board.
3#
4# Note! Dependencies are done automagically by 'make dep', which also
5# removes any old dependencies. DON'T put your own dependencies here
6# unless it's something special (ie not a .c file).
7#
8obj-y += int-handler.o irq.o prom.o reset.o setup.o
diff --git a/arch/mips/momentum/ocelot_3/int-handler.S b/arch/mips/momentum/ocelot_3/int-handler.S
new file mode 100644
index 000000000000..4522f09ed769
--- /dev/null
+++ b/arch/mips/momentum/ocelot_3/int-handler.S
@@ -0,0 +1,137 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: jsun@mvista.com or jsun@junsun.net
7 *
8 * Copyright 2004 PMC-Sierra
9 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
10 *
11 * Copyright (C) 2004 MontaVista Software Inc.
12 * Author: Manish Lachwani, mlachwani@mvista.com
13 *
14 * First-level interrupt dispatcher for Ocelot-3 board.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 */
21#include <asm/asm.h>
22#include <asm/mipsregs.h>
23#include <asm/addrspace.h>
24#include <asm/regdef.h>
25#include <asm/stackframe.h>
26
27/*
28 * First level interrupt dispatcher for Ocelot-3 board
29 */
30 .align 5
31 NESTED(ocelot3_handle_int, PT_SIZE, sp)
32 SAVE_ALL
33 CLI
34 .set at
35
36 mfc0 t0, CP0_CAUSE
37 mfc0 t2, CP0_STATUS
38
39 and t0, t2
40
41 andi t1, t0, STATUSF_IP0 /* sw0 software interrupt (IRQ0) */
42 bnez t1, ll_sw0_irq
43
44 andi t1, t0, STATUSF_IP1 /* sw1 software interrupt (IRQ1) */
45 bnez t1, ll_sw1_irq
46
47 andi t1, t0, STATUSF_IP2 /* int0 hardware line (IRQ2) */
48 bnez t1, ll_pci0slot1_irq
49
50 andi t1, t0, STATUSF_IP3 /* int1 hardware line (IRQ3) */
51 bnez t1, ll_pci0slot2_irq
52
53 andi t1, t0, STATUSF_IP4 /* int2 hardware line (IRQ4) */
54 bnez t1, ll_pci1slot1_irq
55
56 andi t1, t0, STATUSF_IP5 /* int3 hardware line (IRQ5) */
57 bnez t1, ll_pci1slot2_irq
58
59 andi t1, t0, STATUSF_IP6 /* int4 hardware line (IRQ6) */
60 bnez t1, ll_uart_irq
61
62 andi t1, t0, STATUSF_IP7 /* cpu timer (IRQ7) */
63 bnez t1, ll_cputimer_irq
64
65 /* now look at extended interrupts */
66 mfc0 t0, CP0_CAUSE
67 cfc0 t1, CP0_S1_INTCONTROL
68
69 /* shift the mask 8 bits left to line up the bits */
70 sll t2, t1, 8
71
72 and t0, t2
73 srl t0, t0, 16
74
75 andi t1, t0, STATUSF_IP8 /* int6 hardware line (IRQ9) */
76 bnez t1, ll_mv64340_decode_irq
77
78 .set reorder
79
80 /* wrong alarm or masked ... */
81 j spurious_interrupt
82 nop
83 END(ocelot3_handle_int)
84
85 .align 5
86ll_sw0_irq:
87 li a0, 0 /* IRQ 1 */
88 move a1, sp
89 jal do_IRQ
90 j ret_from_irq
91ll_sw1_irq:
92 li a0, 1 /* IRQ 2 */
93 move a1, sp
94 jal do_IRQ
95 j ret_from_irq
96
97ll_pci0slot1_irq:
98 li a0, 2 /* IRQ 3 */
99 move a1, sp
100 jal do_IRQ
101 j ret_from_irq
102
103ll_pci0slot2_irq:
104 li a0, 3 /* IRQ 4 */
105 move a1, sp
106 jal do_IRQ
107 j ret_from_irq
108
109ll_pci1slot1_irq:
110 li a0, 4 /* IRQ 5 */
111 move a1, sp
112 jal do_IRQ
113 j ret_from_irq
114
115ll_pci1slot2_irq:
116 li a0, 5 /* IRQ 6 */
117 move a1, sp
118 jal do_IRQ
119 j ret_from_irq
120
121ll_uart_irq:
122 li a0, 6 /* IRQ 7 */
123 move a1, sp
124 jal do_IRQ
125 j ret_from_irq
126
127ll_cputimer_irq:
128 li a0, 7 /* IRQ 8 */
129 move a1, sp
130 jal do_IRQ
131 j ret_from_irq
132
133ll_mv64340_decode_irq:
134 move a0, sp
135 jal ll_mv64340_irq
136 j ret_from_irq
137
diff --git a/arch/mips/momentum/ocelot_3/irq.c b/arch/mips/momentum/ocelot_3/irq.c
new file mode 100644
index 000000000000..42464dbd4ad2
--- /dev/null
+++ b/arch/mips/momentum/ocelot_3/irq.c
@@ -0,0 +1,81 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
9 *
10 * Copyright 2004 PMC-Sierra
11 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 *
33 * Copyright (C) 2004 MontaVista Software Inc.
34 * Author: Manish Lachwani, mlachwani@mvista.com
35 *
36 */
37#include <linux/errno.h>
38#include <linux/init.h>
39#include <linux/kernel_stat.h>
40#include <linux/module.h>
41#include <linux/signal.h>
42#include <linux/sched.h>
43#include <linux/types.h>
44#include <linux/interrupt.h>
45#include <linux/ioport.h>
46#include <linux/timex.h>
47#include <linux/slab.h>
48#include <linux/random.h>
49#include <asm/bitops.h>
50#include <asm/bootinfo.h>
51#include <asm/io.h>
52#include <asm/irq.h>
53#include <asm/mipsregs.h>
54#include <asm/system.h>
55
56extern asmlinkage void ocelot3_handle_int(void);
57
58static struct irqaction cascade_mv64340 = {
59 no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
60};
61
62void __init arch_init_irq(void)
63{
64 /*
65 * Clear all of the interrupts while we change the able around a bit.
66 * int-handler is not on bootstrap
67 */
68 clear_c0_status(ST0_IM | ST0_BEV);
69
70 /* Sets the first-level interrupt dispatcher. */
71 set_except_vector(0, ocelot3_handle_int);
72 mips_cpu_irq_init(0);
73 rm7k_cpu_irq_init(8);
74
75 /* set up the cascading interrupts */
76 setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */
77 mv64340_irq_init(16);
78
79 set_c0_status(ST0_IM); /* IE in the status register */
80
81}
diff --git a/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h b/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h
new file mode 100644
index 000000000000..227e429fe720
--- /dev/null
+++ b/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h
@@ -0,0 +1,57 @@
1/*
2 * Ocelot-3 Board Register Definitions
3 *
4 * (C) 2002 Momentum Computer Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Louis Hamilton, Red Hat, Inc.
27 * hamilton@redhat.com [MIPS64 modifications]
28 *
29 * Copyright (C) 2004 MontaVista Software Inc.
30 * Author: Manish Lachwani, mlachwani@mvista.com
31 */
32
33#ifndef __OCELOT_3_FPGA_H__
34#define __OCELOT_3_FPGA_H__
35
36#define OCELOT_3_REG_BOARDREV 0x0
37#define OCELOT_3_REG_FPGA_REV 0x1
38#define OCELOT_3_REG_FPGA_TYPE 0x2
39#define OCELOT_3_REG_RESET_STATUS 0x3
40#define OCELOT_3_REG_BOARD_STATUS 0x4
41#define OCELOT_3_REG_CPCI_ID 0x5
42#define OCELOT_3_REG_SET 0x6
43#define OCELOT_3_REG_CLR 0x7
44#define OCELOT_3_REG_EEPROM_MODE 0x9
45#define OCELOT_3_REG_INTMASK 0xa
46#define OCELOT_3_REG_INTSTAT 0xb
47#define OCELOT_3_REG_UART_INTMASK 0xc
48#define OCELOT_3_REG_UART_INTSTAT 0xd
49#define OCELOT_3_REG_INTSET 0xe
50#define OCELOT_3_REG_INTCLR 0xf
51
52extern unsigned long ocelot_fpga_base;
53
54#define OCELOT_FPGA_WRITE(x, y) writeb(x, ocelot_fpga_base + OCELOT_3_REG_##y)
55#define OCELOT_FPGA_READ(x) readb(ocelot_fpga_base + OCELOT_3_REG_##x)
56
57#endif
diff --git a/arch/mips/momentum/ocelot_3/prom.c b/arch/mips/momentum/ocelot_3/prom.c
new file mode 100644
index 000000000000..89c17a0c0bed
--- /dev/null
+++ b/arch/mips/momentum/ocelot_3/prom.c
@@ -0,0 +1,248 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Louis Hamilton, Red Hat, Inc.
6 * hamilton@redhat.com [MIPS64 modifications]
7 *
8 * Copyright 2004 PMC-Sierra
9 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
10 *
11 * Based on Ocelot Linux port, which is
12 * Copyright 2001 MontaVista Software Inc.
13 * Author: jsun@mvista.com or jsun@junsun.net
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Copyright (C) 2004 MontaVista Software Inc.
21 * Author: Manish Lachwani, mlachwani@mvista.com
22 *
23 */
24#include <linux/config.h>
25#include <linux/init.h>
26#include <linux/bootmem.h>
27#include <linux/mv643xx.h>
28
29#include <asm/addrspace.h>
30#include <asm/bootinfo.h>
31#include <asm/pmon.h>
32#include "ocelot_3_fpga.h"
33
34struct callvectors* debug_vectors;
35extern unsigned long marvell_base;
36extern unsigned long cpu_clock;
37
38#ifdef CONFIG_MV643XX_ETH
39extern unsigned char prom_mac_addr_base[6];
40#endif
41
42const char *get_system_type(void)
43{
44 return "Momentum Ocelot-3";
45}
46
47#ifdef CONFIG_MV643XX_ETH
48void burn_clocks(void)
49{
50 int i;
51
52 /* this loop should burn at least 1us -- this should be plenty */
53 for (i = 0; i < 0x10000; i++)
54 ;
55}
56
57u8 exchange_bit(u8 val, u8 cs)
58{
59 /* place the data */
60 OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
61 burn_clocks();
62
63 /* turn the clock on */
64 OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
65 burn_clocks();
66
67 /* turn the clock off and read-strobe */
68 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
69
70 /* return the data */
71 return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
72}
73
74void get_mac(char dest[6])
75{
76 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
77 int i,j;
78
79 for (i = 0; i < 12; i++)
80 exchange_bit(read_opcode[i], 1);
81
82 for (j = 0; j < 6; j++) {
83 dest[j] = 0;
84 for (i = 0; i < 8; i++) {
85 dest[j] <<= 1;
86 dest[j] |= exchange_bit(0, 1);
87 }
88 }
89
90 /* turn off CS */
91 exchange_bit(0,0);
92}
93#endif
94
95
96#ifdef CONFIG_MIPS64
97
98unsigned long signext(unsigned long addr)
99{
100 addr &= 0xffffffff;
101 return (unsigned long)((int)addr);
102}
103
104void *get_arg(unsigned long args, int arc)
105{
106 unsigned long ul;
107 unsigned char *puc, uc;
108
109 args += (arc * 4);
110 ul = (unsigned long)signext(args);
111 puc = (unsigned char *)ul;
112 if (puc == 0)
113 return (void *)0;
114
115#ifdef CONFIG_CPU_LITTLE_ENDIAN
116 uc = *puc++;
117 ul = (unsigned long)uc;
118 uc = *puc++;
119 ul |= (((unsigned long)uc) << 8);
120 uc = *puc++;
121 ul |= (((unsigned long)uc) << 16);
122 uc = *puc++;
123 ul |= (((unsigned long)uc) << 24);
124#else /* CONFIG_CPU_LITTLE_ENDIAN */
125 uc = *puc++;
126 ul = ((unsigned long)uc) << 24;
127 uc = *puc++;
128 ul |= (((unsigned long)uc) << 16);
129 uc = *puc++;
130 ul |= (((unsigned long)uc) << 8);
131 uc = *puc++;
132 ul |= ((unsigned long)uc);
133#endif /* CONFIG_CPU_LITTLE_ENDIAN */
134 ul = signext(ul);
135 return (void *)ul;
136}
137
138char *arg64(unsigned long addrin, int arg_index)
139{
140 unsigned long args;
141 char *p;
142
143 args = signext(addrin);
144 p = (char *)get_arg(args, arg_index);
145
146 return p;
147}
148#endif /* CONFIG_MIPS64 */
149
150void __init prom_init(void)
151{
152 int argc = fw_arg0;
153 char **arg = (char **) fw_arg1;
154 char **env = (char **) fw_arg2;
155 struct callvectors *cv = (struct callvectors *) fw_arg3;
156 int i;
157
158#ifdef CONFIG_MIPS64
159 char *ptr;
160 printk("prom_init - MIPS64\n");
161
162 /* save the PROM vectors for debugging use */
163 debug_vectors = (struct callvectors *)signext((unsigned long)cv);
164
165 /* arg[0] is "g", the rest is boot parameters */
166 arcs_cmdline[0] = '\0';
167
168 for (i = 1; i < argc; i++) {
169 ptr = (char *)arg64((unsigned long)arg, i);
170 if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
171 sizeof(arcs_cmdline))
172 break;
173 strcat(arcs_cmdline, ptr);
174 strcat(arcs_cmdline, " ");
175 }
176 i = 0;
177
178 while (1) {
179 ptr = (char *)arg64((unsigned long)env, i);
180 if (! ptr)
181 break;
182
183 if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
184 marvell_base = simple_strtol(ptr + strlen("gtbase="),
185 NULL, 16);
186
187 if ((marvell_base & 0xffffffff00000000) == 0)
188 marvell_base |= 0xffffffff00000000;
189
190 printk("marvell_base set to 0x%016lx\n", marvell_base);
191 }
192 if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
193 cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
194 NULL, 10);
195 printk("cpu_clock set to %d\n", cpu_clock);
196 }
197 i++;
198 }
199 printk("arcs_cmdline: %s\n", arcs_cmdline);
200
201#else /* CONFIG_MIPS64 */
202
203 /* save the PROM vectors for debugging use */
204 debug_vectors = cv;
205
206 /* arg[0] is "g", the rest is boot parameters */
207 arcs_cmdline[0] = '\0';
208 for (i = 1; i < argc; i++) {
209 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
210 >= sizeof(arcs_cmdline))
211 break;
212 strcat(arcs_cmdline, arg[i]);
213 strcat(arcs_cmdline, " ");
214 }
215
216 while (*env) {
217 if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
218 marvell_base = simple_strtol(*env + strlen("gtbase="),
219 NULL, 16);
220 }
221 if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
222 cpu_clock = simple_strtol(*env + strlen("cpuclock="),
223 NULL, 10);
224 }
225 env++;
226 }
227#endif /* CONFIG_MIPS64 */
228
229 mips_machgroup = MACH_GROUP_MOMENCO;
230 mips_machtype = MACH_MOMENCO_OCELOT_3;
231
232#ifdef CONFIG_MV643XX_ETH
233 /* get the base MAC address for on-board ethernet ports */
234 get_mac(prom_mac_addr_base);
235#endif
236
237#ifndef CONFIG_MIPS64
238 debug_vectors->printf("Booting Linux kernel...\n");
239#endif
240}
241
242void __init prom_free_prom_memory(void)
243{
244}
245
246void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
247{
248}
diff --git a/arch/mips/momentum/ocelot_3/reset.c b/arch/mips/momentum/ocelot_3/reset.c
new file mode 100644
index 000000000000..72b4423c0864
--- /dev/null
+++ b/arch/mips/momentum/ocelot_3/reset.c
@@ -0,0 +1,59 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 01, 05 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 * Copyright (C) 2002 Momentum Computer Inc.
12 * Author: Matthew Dharm <mdharm@momenco.com>
13 *
14 * Louis Hamilton, Red Hat, Inc.
15 * hamilton@redhat.com [MIPS64 modifications]
16 *
17 * Copyright 2004 PMC-Sierra
18 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
19 *
20 * Copyright (C) 2004 MontaVista Software Inc.
21 * Author: Manish Lachwani, mlachwani@mvista.com
22 */
23#include <linux/sched.h>
24#include <linux/mm.h>
25#include <linux/delay.h>
26#include <asm/io.h>
27#include <asm/pgtable.h>
28#include <asm/processor.h>
29#include <asm/reboot.h>
30#include <asm/system.h>
31
32void momenco_ocelot_restart(char *command)
33{
34 /* base address of timekeeper portion of part */
35 void *nvram = (void *) 0xfc807000L;
36
37 /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
38 writeb(0x84, nvram + 0xff7);
39
40 /* wait for the watchdog to go off */
41 mdelay(100+(1000/16));
42
43 /* if the watchdog fails for some reason, let people know */
44 printk(KERN_NOTICE "Watchdog reset failed\n");
45}
46
47void momenco_ocelot_halt(void)
48{
49 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
50 while (1)
51 __asm__(".set\tmips3\n\t"
52 "wait\n\t"
53 ".set\tmips0");
54}
55
56void momenco_ocelot_power_off(void)
57{
58 momenco_ocelot_halt();
59}
diff --git a/arch/mips/momentum/ocelot_3/setup.c b/arch/mips/momentum/ocelot_3/setup.c
new file mode 100644
index 000000000000..ce2efcbab7aa
--- /dev/null
+++ b/arch/mips/momentum/ocelot_3/setup.c
@@ -0,0 +1,398 @@
1/*
2 * setup.c
3 *
4 * BRIEF MODULE DESCRIPTION
5 * Momentum Computer Ocelot-3 board dependent boot routines
6 *
7 * Copyright (C) 1996, 1997, 01, 05 Ralf Baechle
8 * Copyright (C) 2000 RidgeRun, Inc.
9 * Copyright (C) 2001 Red Hat, Inc.
10 * Copyright (C) 2002 Momentum Computer
11 *
12 * Author: Matthew Dharm, Momentum Computer
13 * mdharm@momenco.com
14 *
15 * Louis Hamilton, Red Hat, Inc.
16 * hamilton@redhat.com [MIPS64 modifications]
17 *
18 * Author: RidgeRun, Inc.
19 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
20 *
21 * Copyright 2001 MontaVista Software Inc.
22 * Author: jsun@mvista.com or jsun@junsun.net
23 *
24 * Copyright 2004 PMC-Sierra
25 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
26 *
27 * Copyright (C) 2004 MontaVista Software Inc.
28 * Author: Manish Lachwani, mlachwani@mvista.com
29 *
30 * This program is free software; you can redistribute it and/or modify it
31 * under the terms of the GNU General Public License as published by the
32 * Free Software Foundation; either version 2 of the License, or (at your
33 * option) any later version.
34 *
35 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
36 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
37 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
38 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
40 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
41 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
42 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
44 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 * You should have received a copy of the GNU General Public License along
47 * with this program; if not, write to the Free Software Foundation, Inc.,
48 * 675 Mass Ave, Cambridge, MA 02139, USA.
49 */
50#include <linux/init.h>
51#include <linux/kernel.h>
52#include <linux/types.h>
53#include <linux/mc146818rtc.h>
54#include <linux/ioport.h>
55#include <linux/interrupt.h>
56#include <linux/pci.h>
57#include <linux/timex.h>
58#include <linux/bootmem.h>
59#include <linux/mv643xx.h>
60#include <asm/time.h>
61#include <asm/page.h>
62#include <asm/bootinfo.h>
63#include <asm/io.h>
64#include <asm/irq.h>
65#include <asm/pci.h>
66#include <asm/processor.h>
67#include <asm/ptrace.h>
68#include <asm/reboot.h>
69#include <asm/mc146818rtc.h>
70#include <asm/tlbflush.h>
71#include "ocelot_3_fpga.h"
72
73/* Marvell Discovery Register Base */
74unsigned long marvell_base = (signed)0xf4000000;
75
76/* CPU clock */
77unsigned long cpu_clock;
78
79/* RTC/NVRAM */
80unsigned char* rtc_base = (unsigned char*)(signed)0xfc800000;
81
82/* FPGA Base */
83unsigned long ocelot_fpga_base = (signed)0xfc000000;
84
85/* Serial base */
86unsigned long uart_base = (signed)0xfd000000;
87
88/*
89 * Marvell Discovery SRAM. This is one place where Ethernet
90 * Tx and Rx descriptors can be placed to improve performance
91 */
92extern unsigned long mv64340_sram_base;
93
94/* These functions are used for rebooting or halting the machine*/
95extern void momenco_ocelot_restart(char *command);
96extern void momenco_ocelot_halt(void);
97extern void momenco_ocelot_power_off(void);
98
99void momenco_time_init(void);
100static char reset_reason;
101
102void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
103 unsigned long entryhi, unsigned long pagemask);
104
105static inline unsigned long ENTRYLO(unsigned long paddr)
106{
107 return ((paddr & PAGE_MASK) |
108 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
109 _CACHE_UNCACHED)) >> 6;
110}
111
112void __init bus_error_init(void)
113{
114 /* nothing */
115}
116
117/*
118 * setup code for a handoff from a version 2 PMON 2000 PROM
119 */
120void setup_wired_tlb_entries(void)
121{
122 write_c0_wired(0);
123 local_flush_tlb_all();
124
125 /* marvell and extra space */
126 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), (signed)0xf4000000, PM_64K);
127
128 /* fpga, rtc, and uart */
129 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), (signed)0xfc000000, PM_16M);
130}
131
132#define CONV_BCD_TO_BIN(val) (((val) & 0xf) + (((val) >> 4) * 10))
133#define CONV_BIN_TO_BCD(val) (((val) % 10) + (((val) / 10) << 4))
134
135unsigned long m48t37y_get_time(void)
136{
137 unsigned int year, month, day, hour, min, sec;
138
139 /* stop the update */
140 rtc_base[0x7ff8] = 0x40;
141
142 year = CONV_BCD_TO_BIN(rtc_base[0x7fff]);
143 year += CONV_BCD_TO_BIN(rtc_base[0x7ff1]) * 100;
144
145 month = CONV_BCD_TO_BIN(rtc_base[0x7ffe]);
146
147 day = CONV_BCD_TO_BIN(rtc_base[0x7ffd]);
148
149 hour = CONV_BCD_TO_BIN(rtc_base[0x7ffb]);
150 min = CONV_BCD_TO_BIN(rtc_base[0x7ffa]);
151 sec = CONV_BCD_TO_BIN(rtc_base[0x7ff9]);
152
153 /* start the update */
154 rtc_base[0x7ff8] = 0x00;
155
156 return mktime(year, month, day, hour, min, sec);
157}
158
159int m48t37y_set_time(unsigned long sec)
160{
161 struct rtc_time tm;
162
163 /* convert to a more useful format -- note months count from 0 */
164 to_tm(sec, &tm);
165 tm.tm_mon += 1;
166
167 /* enable writing */
168 rtc_base[0x7ff8] = 0x80;
169
170 /* year */
171 rtc_base[0x7fff] = CONV_BIN_TO_BCD(tm.tm_year % 100);
172 rtc_base[0x7ff1] = CONV_BIN_TO_BCD(tm.tm_year / 100);
173
174 /* month */
175 rtc_base[0x7ffe] = CONV_BIN_TO_BCD(tm.tm_mon);
176
177 /* day */
178 rtc_base[0x7ffd] = CONV_BIN_TO_BCD(tm.tm_mday);
179
180 /* hour/min/sec */
181 rtc_base[0x7ffb] = CONV_BIN_TO_BCD(tm.tm_hour);
182 rtc_base[0x7ffa] = CONV_BIN_TO_BCD(tm.tm_min);
183 rtc_base[0x7ff9] = CONV_BIN_TO_BCD(tm.tm_sec);
184
185 /* day of week -- not really used, but let's keep it up-to-date */
186 rtc_base[0x7ffc] = CONV_BIN_TO_BCD(tm.tm_wday + 1);
187
188 /* disable writing */
189 rtc_base[0x7ff8] = 0x00;
190
191 return 0;
192}
193
194void momenco_timer_setup(struct irqaction *irq)
195{
196 setup_irq(7, irq); /* Timer interrupt, unmask status IM7 */
197}
198
199void momenco_time_init(void)
200{
201 setup_wired_tlb_entries();
202
203 /*
204 * Ocelot-3 board has been built with both
205 * the Rm7900 and the Rm7065C
206 */
207 mips_hpt_frequency = cpu_clock / 2;
208 board_timer_setup = momenco_timer_setup;
209
210 rtc_get_time = m48t37y_get_time;
211 rtc_set_time = m48t37y_set_time;
212}
213
214/*
215 * PCI Support for Ocelot-3
216 */
217
218/* Bus #0 IO and MEM space */
219#define OCELOT_3_PCI_IO_0_START 0xe0000000
220#define OCELOT_3_PCI_IO_0_SIZE 0x08000000
221#define OCELOT_3_PCI_MEM_0_START 0xc0000000
222#define OCELOT_3_PCI_MEM_0_SIZE 0x10000000
223
224/* Bus #1 IO and MEM space */
225#define OCELOT_3_PCI_IO_1_START 0xe8000000
226#define OCELOT_3_PCI_IO_1_SIZE 0x08000000
227#define OCELOT_3_PCI_MEM_1_START 0xd0000000
228#define OCELOT_3_PCI_MEM_1_SIZE 0x10000000
229
230static struct resource mv_pci_io_mem0_resource = {
231 .name = "MV64340 PCI0 IO MEM",
232 .start = OCELOT_3_PCI_IO_0_START,
233 .end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE - 1,
234 .flags = IORESOURCE_IO,
235};
236
237static struct resource mv_pci_io_mem1_resource = {
238 .name = "MV64340 PCI1 IO MEM",
239 .start = OCELOT_3_PCI_IO_1_START,
240 .end = OCELOT_3_PCI_IO_1_START + OCELOT_3_PCI_IO_1_SIZE - 1,
241 .flags = IORESOURCE_IO,
242};
243
244static struct resource mv_pci_mem0_resource = {
245 .name = "MV64340 PCI0 MEM",
246 .start = OCELOT_3_PCI_MEM_0_START,
247 .end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE - 1,
248 .flags = IORESOURCE_MEM,
249};
250
251static struct resource mv_pci_mem1_resource = {
252 .name = "MV64340 PCI1 MEM",
253 .start = OCELOT_3_PCI_MEM_1_START,
254 .end = OCELOT_3_PCI_MEM_1_START + OCELOT_3_PCI_MEM_1_SIZE - 1,
255 .flags = IORESOURCE_MEM,
256};
257
258static struct mv_pci_controller mv_bus0_controller = {
259 .pcic = {
260 .pci_ops = &mv_pci_ops,
261 .mem_resource = &mv_pci_mem0_resource,
262 .io_resource = &mv_pci_io_mem0_resource,
263 },
264 .config_addr = MV64340_PCI_0_CONFIG_ADDR,
265 .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
266};
267
268static struct mv_pci_controller mv_bus1_controller = {
269 .pcic = {
270 .pci_ops = &mv_pci_ops,
271 .mem_resource = &mv_pci_mem1_resource,
272 .io_resource = &mv_pci_io_mem1_resource,
273 },
274 .config_addr = MV64340_PCI_1_CONFIG_ADDR,
275 .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
276};
277
278static __init int __init ja_pci_init(void)
279{
280 uint32_t enable;
281 extern int pci_probe_only;
282
283 /* PMON will assign PCI resources */
284 pci_probe_only = 1;
285
286 enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
287 /*
288 * We require at least one enabled I/O or PCI memory window or we
289 * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
290 */
291 if (enable & (0x01 << 9) || enable & (0x01 << 10))
292 register_pci_controller(&mv_bus0_controller.pcic);
293
294 if (enable & (0x01 << 14) || enable & (0x01 << 15))
295 register_pci_controller(&mv_bus1_controller.pcic);
296
297 ioport_resource.end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE +
298 OCELOT_3_PCI_IO_1_SIZE - 1;
299
300 iomem_resource.end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE +
301 OCELOT_3_PCI_MEM_1_SIZE - 1;
302
303 set_io_port_base(OCELOT_3_PCI_IO_0_START); /* mips_io_port_base */
304
305 return 0;
306}
307
308arch_initcall(ja_pci_init);
309
310static int __init momenco_ocelot_3_setup(void)
311{
312 unsigned int tmpword;
313
314 board_time_init = momenco_time_init;
315
316 _machine_restart = momenco_ocelot_restart;
317 _machine_halt = momenco_ocelot_halt;
318 _machine_power_off = momenco_ocelot_power_off;
319
320 /* Wired TLB entries */
321 setup_wired_tlb_entries();
322
323 /* shut down ethernet ports, just to be sure our memory doesn't get
324 * corrupted by random ethernet traffic.
325 */
326 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
327 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
328 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
329 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
330 do {}
331 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
332 do {}
333 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
334 do {}
335 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
336 do {}
337 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
338 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
339 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
340 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
341 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
342
343 /* Turn off the Bit-Error LED */
344 OCELOT_FPGA_WRITE(0x80, CLR);
345
346 tmpword = OCELOT_FPGA_READ(BOARDREV);
347 if (tmpword < 26)
348 printk("Momenco Ocelot-3: Board Assembly Rev. %c\n",
349 'A'+tmpword);
350 else
351 printk("Momenco Ocelot-3: Board Assembly Revision #0x%x\n",
352 tmpword);
353
354 tmpword = OCELOT_FPGA_READ(FPGA_REV);
355 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
356 tmpword = OCELOT_FPGA_READ(RESET_STATUS);
357 printk("Reset reason: 0x%x\n", tmpword);
358 switch (tmpword) {
359 case 0x1:
360 printk(" - Power-up reset\n");
361 break;
362 case 0x2:
363 printk(" - Push-button reset\n");
364 break;
365 case 0x4:
366 printk(" - cPCI bus reset\n");
367 break;
368 case 0x8:
369 printk(" - Watchdog reset\n");
370 break;
371 case 0x10:
372 printk(" - Software reset\n");
373 break;
374 default:
375 printk(" - Unknown reset cause\n");
376 }
377 reset_reason = tmpword;
378 OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
379
380 tmpword = OCELOT_FPGA_READ(CPCI_ID);
381 printk("cPCI ID register: 0x%02x\n", tmpword);
382 printk(" - Slot number: %d\n", tmpword & 0x1f);
383 printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
384 printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
385
386 tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
387 printk("Board Status register: 0x%02x\n", tmpword);
388 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
389 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
390 printk(" - L3 cache size: %d MB\n", (1<<((tmpword&12) >> 2))&~1);
391
392 /* Support for 128 MB memory */
393 add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM);
394
395 return 0;
396}
397
398early_initcall(momenco_ocelot_3_setup);
diff --git a/arch/mips/momentum/ocelot_c/Makefile b/arch/mips/momentum/ocelot_c/Makefile
new file mode 100644
index 000000000000..91240777f978
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for Momentum Computer's Ocelot-C and -CS boards.
3#
4
5obj-y += cpci-irq.o int-handler.o irq.o prom.o reset.o \
6 setup.o uart-irq.o
7
8obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
new file mode 100644
index 000000000000..dea48b3ad687
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/cpci-irq.c
@@ -0,0 +1,153 @@
1/*
2 * Copyright 2002 Momentum Computer
3 * Author: mdharm@momenco.com
4 *
5 * arch/mips/momentum/ocelot_c/cpci-irq.c
6 * Interrupt routines for cpci. Interrupt numbers are assigned from
7 * CPCI_IRQ_BASE to CPCI_IRQ_BASE+8 (8 interrupt sources).
8 *
9 * Note that the high-level software will need to be careful about using
10 * these interrupts. If this board is asserting a cPCI interrupt, it will
11 * also see the asserted interrupt. Care must be taken to avoid an
12 * interrupt flood.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19
20#include <linux/module.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/kernel.h>
24#include <asm/ptrace.h>
25#include <linux/sched.h>
26#include <linux/kernel_stat.h>
27#include <asm/io.h>
28#include "ocelot_c_fpga.h"
29
30#define CPCI_IRQ_BASE 8
31
32static inline int ls1bit8(unsigned int x)
33{
34 int b = 7, s;
35
36 s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
37 s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
38 s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
39
40 return b;
41}
42
43/* mask off an interrupt -- 0 is enable, 1 is disable */
44static inline void mask_cpci_irq(unsigned int irq)
45{
46 uint32_t value;
47
48 value = OCELOT_FPGA_READ(INTMASK);
49 value |= 1 << (irq - CPCI_IRQ_BASE);
50 OCELOT_FPGA_WRITE(value, INTMASK);
51
52 /* read the value back to assure that it's really been written */
53 value = OCELOT_FPGA_READ(INTMASK);
54}
55
56/* unmask an interrupt -- 0 is enable, 1 is disable */
57static inline void unmask_cpci_irq(unsigned int irq)
58{
59 uint32_t value;
60
61 value = OCELOT_FPGA_READ(INTMASK);
62 value &= ~(1 << (irq - CPCI_IRQ_BASE));
63 OCELOT_FPGA_WRITE(value, INTMASK);
64
65 /* read the value back to assure that it's really been written */
66 value = OCELOT_FPGA_READ(INTMASK);
67}
68
69/*
70 * Enables the IRQ in the FPGA
71 */
72static void enable_cpci_irq(unsigned int irq)
73{
74 unmask_cpci_irq(irq);
75}
76
77/*
78 * Initialize the IRQ in the FPGA
79 */
80static unsigned int startup_cpci_irq(unsigned int irq)
81{
82 unmask_cpci_irq(irq);
83 return 0;
84}
85
86/*
87 * Disables the IRQ in the FPGA
88 */
89static void disable_cpci_irq(unsigned int irq)
90{
91 mask_cpci_irq(irq);
92}
93
94/*
95 * Masks and ACKs an IRQ
96 */
97static void mask_and_ack_cpci_irq(unsigned int irq)
98{
99 mask_cpci_irq(irq);
100}
101
102/*
103 * End IRQ processing
104 */
105static void end_cpci_irq(unsigned int irq)
106{
107 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
108 unmask_cpci_irq(irq);
109}
110
111/*
112 * Interrupt handler for interrupts coming from the FPGA chip.
113 * It could be built in ethernet ports etc...
114 */
115void ll_cpci_irq(struct pt_regs *regs)
116{
117 unsigned int irq_src, irq_mask;
118
119 /* read the interrupt status registers */
120 irq_src = OCELOT_FPGA_READ(INTSTAT);
121 irq_mask = OCELOT_FPGA_READ(INTMASK);
122
123 /* mask for just the interrupts we want */
124 irq_src &= ~irq_mask;
125
126 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE, regs);
127}
128
129#define shutdown_cpci_irq disable_cpci_irq
130
131struct hw_interrupt_type cpci_irq_type = {
132 "CPCI/FPGA",
133 startup_cpci_irq,
134 shutdown_cpci_irq,
135 enable_cpci_irq,
136 disable_cpci_irq,
137 mask_and_ack_cpci_irq,
138 end_cpci_irq,
139 NULL
140};
141
142void cpci_irq_init(void)
143{
144 int i;
145
146 /* Reset irq handlers pointers to NULL */
147 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) {
148 irq_desc[i].status = IRQ_DISABLED;
149 irq_desc[i].action = 0;
150 irq_desc[i].depth = 2;
151 irq_desc[i].handler = &cpci_irq_type;
152 }
153}
diff --git a/arch/mips/momentum/ocelot_c/dbg_io.c b/arch/mips/momentum/ocelot_c/dbg_io.c
new file mode 100644
index 000000000000..8720bccfdea2
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/dbg_io.c
@@ -0,0 +1,126 @@
1#include <linux/config.h>
2
3#ifdef CONFIG_KGDB
4
5#include <asm/serial.h> /* For the serial port location and base baud */
6
7/* --- CONFIG --- */
8
9typedef unsigned char uint8;
10typedef unsigned int uint32;
11
12/* --- END OF CONFIG --- */
13
14#define UART16550_BAUD_2400 2400
15#define UART16550_BAUD_4800 4800
16#define UART16550_BAUD_9600 9600
17#define UART16550_BAUD_19200 19200
18#define UART16550_BAUD_38400 38400
19#define UART16550_BAUD_57600 57600
20#define UART16550_BAUD_115200 115200
21
22#define UART16550_PARITY_NONE 0
23#define UART16550_PARITY_ODD 0x08
24#define UART16550_PARITY_EVEN 0x18
25#define UART16550_PARITY_MARK 0x28
26#define UART16550_PARITY_SPACE 0x38
27
28#define UART16550_DATA_5BIT 0x0
29#define UART16550_DATA_6BIT 0x1
30#define UART16550_DATA_7BIT 0x2
31#define UART16550_DATA_8BIT 0x3
32
33#define UART16550_STOP_1BIT 0x0
34#define UART16550_STOP_2BIT 0x4
35
36/* ----------------------------------------------------- */
37
38/* === CONFIG === */
39
40/* [jsun] we use the second serial port for kdb */
41#define BASE OCELOT_SERIAL1_BASE
42#define MAX_BAUD OCELOT_BASE_BAUD
43
44/* === END OF CONFIG === */
45
46#define REG_OFFSET 4
47
48/* register offset */
49#define OFS_RCV_BUFFER 0
50#define OFS_TRANS_HOLD 0
51#define OFS_SEND_BUFFER 0
52#define OFS_INTR_ENABLE (1*REG_OFFSET)
53#define OFS_INTR_ID (2*REG_OFFSET)
54#define OFS_DATA_FORMAT (3*REG_OFFSET)
55#define OFS_LINE_CONTROL (3*REG_OFFSET)
56#define OFS_MODEM_CONTROL (4*REG_OFFSET)
57#define OFS_RS232_OUTPUT (4*REG_OFFSET)
58#define OFS_LINE_STATUS (5*REG_OFFSET)
59#define OFS_MODEM_STATUS (6*REG_OFFSET)
60#define OFS_RS232_INPUT (6*REG_OFFSET)
61#define OFS_SCRATCH_PAD (7*REG_OFFSET)
62
63#define OFS_DIVISOR_LSB (0*REG_OFFSET)
64#define OFS_DIVISOR_MSB (1*REG_OFFSET)
65
66
67/* memory-mapped read/write of the port */
68#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
69#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
70
71void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
72{
73 /* disable interrupts */
74 UART16550_WRITE(OFS_INTR_ENABLE, 0);
75
76 /* set up buad rate */
77 {
78 uint32 divisor;
79
80 /* set DIAB bit */
81 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
82
83 /* set divisor */
84 divisor = MAX_BAUD / baud;
85 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
86 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
87
88 /* clear DIAB bit */
89 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
90 }
91
92 /* set data format */
93 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
94}
95
96static int remoteDebugInitialized = 0;
97
98uint8 getDebugChar(void)
99{
100 if (!remoteDebugInitialized) {
101 remoteDebugInitialized = 1;
102 debugInit(UART16550_BAUD_38400,
103 UART16550_DATA_8BIT,
104 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
105 }
106
107 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
108 return UART16550_READ(OFS_RCV_BUFFER);
109}
110
111
112int putDebugChar(uint8 byte)
113{
114 if (!remoteDebugInitialized) {
115 remoteDebugInitialized = 1;
116 debugInit(UART16550_BAUD_38400,
117 UART16550_DATA_8BIT,
118 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
119 }
120
121 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
122 UART16550_WRITE(OFS_SEND_BUFFER, byte);
123 return 1;
124}
125
126#endif
diff --git a/arch/mips/momentum/ocelot_c/int-handler.S b/arch/mips/momentum/ocelot_c/int-handler.S
new file mode 100644
index 000000000000..2f2430648abc
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/int-handler.S
@@ -0,0 +1,102 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: jsun@mvista.com or jsun@junsun.net
7 *
8 * First-level interrupt dispatcher for Ocelot-CS board.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#include <asm/asm.h>
16#include <asm/mipsregs.h>
17#include <asm/addrspace.h>
18#include <asm/regdef.h>
19#include <asm/stackframe.h>
20#include "ocelot_c_fpga.h"
21
22/*
23 * First level interrupt dispatcher for Ocelot-CS board
24 */
25 .align 5
26 NESTED(ocelot_handle_int, PT_SIZE, sp)
27 SAVE_ALL
28 CLI
29 .set at
30 mfc0 t0, CP0_CAUSE
31 mfc0 t2, CP0_STATUS
32
33 and t0, t2
34
35 andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */
36 bnez t1, ll_sw0_irq
37 andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */
38 bnez t1, ll_sw1_irq
39 andi t1, t0, STATUSF_IP2 /* int0 hardware line */
40 bnez t1, ll_scsi_irq
41 andi t1, t0, STATUSF_IP3 /* int1 hardware line */
42 bnez t1, ll_uart_decode_irq
43 andi t1, t0, STATUSF_IP4 /* int2 hardware line */
44 bnez t1, ll_pmc_irq
45 andi t1, t0, STATUSF_IP5 /* int3 hardware line */
46 bnez t1, ll_cpci_decode_irq
47 andi t1, t0, STATUSF_IP6 /* int4 hardware line */
48 bnez t1, ll_mv64340_decode_irq
49 andi t1, t0, STATUSF_IP7 /* cpu timer */
50 bnez t1, ll_cputimer_irq
51
52 .set reorder
53
54 /* wrong alarm or masked ... */
55 j spurious_interrupt
56 nop
57 END(ocelot_handle_int)
58
59 .align 5
60ll_sw0_irq:
61 li a0, 0
62 move a1, sp
63 jal do_IRQ
64 j ret_from_irq
65ll_sw1_irq:
66 li a0, 1
67 move a1, sp
68 jal do_IRQ
69 j ret_from_irq
70ll_scsi_irq:
71 li a0, 2
72 move a1, sp
73 jal do_IRQ
74 j ret_from_irq
75
76ll_uart_decode_irq:
77 move a0, sp
78 jal ll_uart_irq
79 j ret_from_irq
80
81ll_pmc_irq:
82 li a0, 4
83 move a1, sp
84 jal do_IRQ
85 j ret_from_irq
86
87ll_cpci_decode_irq:
88 move a0, sp
89 jal ll_cpci_irq
90 j ret_from_irq
91
92ll_mv64340_decode_irq:
93 move a0, sp
94 jal ll_mv64340_irq
95 j ret_from_irq
96
97ll_cputimer_irq:
98 li a0, 7
99 move a1, sp
100 jal do_IRQ
101 j ret_from_irq
102
diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c
new file mode 100644
index 000000000000..300fe8e4fbe8
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/irq.c
@@ -0,0 +1,83 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 *
30 */
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/kernel_stat.h>
34#include <linux/module.h>
35#include <linux/signal.h>
36#include <linux/sched.h>
37#include <linux/types.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/timex.h>
41#include <linux/slab.h>
42#include <linux/random.h>
43#include <linux/bitops.h>
44#include <asm/bootinfo.h>
45#include <asm/io.h>
46#include <asm/irq_cpu.h>
47#include <asm/mipsregs.h>
48#include <asm/mv64340.h>
49#include <asm/system.h>
50
51extern asmlinkage void ocelot_handle_int(void);
52extern void uart_irq_init(void);
53extern void cpci_irq_init(void);
54
55static struct irqaction cascade_fpga = {
56 no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via FPGA", NULL, NULL
57};
58
59static struct irqaction cascade_mv64340 = {
60 no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
61};
62
63void __init arch_init_irq(void)
64{
65 /*
66 * Clear all of the interrupts while we change the able around a bit.
67 * int-handler is not on bootstrap
68 */
69 clear_c0_status(ST0_IM);
70
71 /* Sets the first-level interrupt dispatcher. */
72 set_except_vector(0, ocelot_handle_int);
73 mips_cpu_irq_init(0);
74
75 /* set up the cascading interrupts */
76 setup_irq(3, &cascade_fpga);
77 setup_irq(5, &cascade_fpga);
78 setup_irq(6, &cascade_mv64340);
79
80 mv64340_irq_init(16);
81 uart_irq_init();
82 cpci_irq_init();
83}
diff --git a/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h b/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
new file mode 100644
index 000000000000..a6cf7a7959b3
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
@@ -0,0 +1,60 @@
1/*
2 * Ocelot-C Board Register Definitions
3 *
4 * (C) 2002 Momentum Computer Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Louis Hamilton, Red Hat, Inc.
27 * hamilton@redhat.com [MIPS64 modifications]
28 */
29
30#ifndef __OCELOT_C_FPGA_H__
31#define __OCELOT_C_FPGA_H__
32
33#include <linux/config.h>
34
35#ifdef CONFIG_MIPS64
36#define OCELOT_C_CS0_ADDR (0xfffffffffc000000)
37#else
38#define OCELOT_C_CS0_ADDR (0xfc000000)
39#endif
40
41#define OCELOT_C_REG_BOARDREV 0x0
42#define OCELOT_C_REG_FPGA_REV 0x1
43#define OCELOT_C_REG_FPGA_TYPE 0x2
44#define OCELOT_C_REG_RESET_STATUS 0x3
45#define OCELOT_C_REG_BOARD_STATUS 0x4
46#define OCELOT_C_REG_CPCI_ID 0x5
47#define OCELOT_C_REG_SET 0x6
48#define OCELOT_C_REG_CLR 0x7
49#define OCELOT_C_REG_EEPROM_MODE 0x9
50#define OCELOT_C_REG_INTMASK 0xa
51#define OCELOT_C_REG_INTSTAT 0xb
52#define OCELOT_C_REG_UART_INTMASK 0xc
53#define OCELOT_C_REG_UART_INTSTAT 0xd
54#define OCELOT_C_REG_INTSET 0xe
55#define OCELOT_C_REG_INTCLR 0xf
56
57#define OCELOT_FPGA_WRITE(x, y) writeb(x, OCELOT_C_CS0_ADDR + OCELOT_C_REG_##y)
58#define OCELOT_FPGA_READ(x) readb(OCELOT_C_CS0_ADDR + OCELOT_C_REG_##x)
59
60#endif
diff --git a/arch/mips/momentum/ocelot_c/prom.c b/arch/mips/momentum/ocelot_c/prom.c
new file mode 100644
index 000000000000..49ac302d8901
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/prom.c
@@ -0,0 +1,243 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Louis Hamilton, Red Hat, Inc.
6 * hamilton@redhat.com [MIPS64 modifications]
7 *
8 * Based on Ocelot Linux port, which is
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: jsun@mvista.com or jsun@junsun.net
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#include <linux/config.h>
18#include <linux/init.h>
19#include <linux/mm.h>
20#include <linux/sched.h>
21#include <linux/bootmem.h>
22
23#include <asm/addrspace.h>
24#include <asm/bootinfo.h>
25#include <asm/mv64340.h>
26#include <asm/pmon.h>
27
28#include "ocelot_c_fpga.h"
29
30struct callvectors* debug_vectors;
31
32extern unsigned long marvell_base;
33extern unsigned long cpu_clock;
34
35#ifdef CONFIG_MV643XX_ETH
36extern unsigned char prom_mac_addr_base[6];
37#endif
38
39const char *get_system_type(void)
40{
41#ifdef CONFIG_CPU_SR71000
42 return "Momentum Ocelot-CS";
43#else
44 return "Momentum Ocelot-C";
45#endif
46}
47
48#ifdef CONFIG_MV643XX_ETH
49static void burn_clocks(void)
50{
51 int i;
52
53 /* this loop should burn at least 1us -- this should be plenty */
54 for (i = 0; i < 0x10000; i++)
55 ;
56}
57
58static u8 exchange_bit(u8 val, u8 cs)
59{
60 /* place the data */
61 OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
62 burn_clocks();
63
64 /* turn the clock on */
65 OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
66 burn_clocks();
67
68 /* turn the clock off and read-strobe */
69 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
70
71 /* return the data */
72 return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
73}
74
75void get_mac(char dest[6])
76{
77 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
78 int i,j;
79
80 for (i = 0; i < 12; i++)
81 exchange_bit(read_opcode[i], 1);
82
83 for (j = 0; j < 6; j++) {
84 dest[j] = 0;
85 for (i = 0; i < 8; i++) {
86 dest[j] <<= 1;
87 dest[j] |= exchange_bit(0, 1);
88 }
89 }
90
91 /* turn off CS */
92 exchange_bit(0,0);
93}
94#endif
95
96
97#ifdef CONFIG_MIPS64
98
99unsigned long signext(unsigned long addr)
100{
101 addr &= 0xffffffff;
102 return (unsigned long)((int)addr);
103}
104
105void *get_arg(unsigned long args, int arc)
106{
107 unsigned long ul;
108 unsigned char *puc, uc;
109
110 args += (arc * 4);
111 ul = (unsigned long)signext(args);
112 puc = (unsigned char *)ul;
113 if (puc == 0)
114 return (void *)0;
115
116#ifdef CONFIG_CPU_LITTLE_ENDIAN
117 uc = *puc++;
118 ul = (unsigned long)uc;
119 uc = *puc++;
120 ul |= (((unsigned long)uc) << 8);
121 uc = *puc++;
122 ul |= (((unsigned long)uc) << 16);
123 uc = *puc++;
124 ul |= (((unsigned long)uc) << 24);
125#else /* CONFIG_CPU_LITTLE_ENDIAN */
126 uc = *puc++;
127 ul = ((unsigned long)uc) << 24;
128 uc = *puc++;
129 ul |= (((unsigned long)uc) << 16);
130 uc = *puc++;
131 ul |= (((unsigned long)uc) << 8);
132 uc = *puc++;
133 ul |= ((unsigned long)uc);
134#endif /* CONFIG_CPU_LITTLE_ENDIAN */
135 ul = signext(ul);
136 return (void *)ul;
137}
138
139char *arg64(unsigned long addrin, int arg_index)
140{
141 unsigned long args;
142 char *p;
143 args = signext(addrin);
144 p = (char *)get_arg(args, arg_index);
145 return p;
146}
147#endif /* CONFIG_MIPS64 */
148
149
150void __init prom_init(void)
151{
152 int argc = fw_arg0;
153 char **arg = (char **) fw_arg1;
154 char **env = (char **) fw_arg2;
155 struct callvectors *cv = (struct callvectors *) fw_arg3;
156 int i;
157
158#ifdef CONFIG_MIPS64
159 char *ptr;
160
161 printk("prom_init - MIPS64\n");
162 /* save the PROM vectors for debugging use */
163 debug_vectors = (struct callvectors *)signext((unsigned long)cv);
164
165 /* arg[0] is "g", the rest is boot parameters */
166 arcs_cmdline[0] = '\0';
167
168 for (i = 1; i < argc; i++) {
169 ptr = (char *)arg64((unsigned long)arg, i);
170 if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
171 sizeof(arcs_cmdline))
172 break;
173 strcat(arcs_cmdline, ptr);
174 strcat(arcs_cmdline, " ");
175 }
176 i = 0;
177 while (1) {
178 ptr = (char *)arg64((unsigned long)env, i);
179 if (! ptr)
180 break;
181
182 if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
183 marvell_base = simple_strtol(ptr + strlen("gtbase="),
184 NULL, 16);
185
186 if ((marvell_base & 0xffffffff00000000) == 0)
187 marvell_base |= 0xffffffff00000000;
188
189 printk("marvell_base set to 0x%016lx\n", marvell_base);
190 }
191 if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
192 cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
193 NULL, 10);
194 printk("cpu_clock set to %d\n", cpu_clock);
195 }
196 i++;
197 }
198 printk("arcs_cmdline: %s\n", arcs_cmdline);
199
200#else /* CONFIG_MIPS64 */
201 /* save the PROM vectors for debugging use */
202 debug_vectors = cv;
203
204 /* arg[0] is "g", the rest is boot parameters */
205 arcs_cmdline[0] = '\0';
206 for (i = 1; i < argc; i++) {
207 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
208 >= sizeof(arcs_cmdline))
209 break;
210 strcat(arcs_cmdline, arg[i]);
211 strcat(arcs_cmdline, " ");
212 }
213
214 while (*env) {
215 if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
216 marvell_base = simple_strtol(*env + strlen("gtbase="),
217 NULL, 16);
218 }
219 if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
220 cpu_clock = simple_strtol(*env + strlen("cpuclock="),
221 NULL, 10);
222 }
223 env++;
224 }
225#endif /* CONFIG_MIPS64 */
226
227 mips_machgroup = MACH_GROUP_MOMENCO;
228 mips_machtype = MACH_MOMENCO_OCELOT_C;
229
230#ifdef CONFIG_MV643XX_ETH
231 /* get the base MAC address for on-board ethernet ports */
232 get_mac(prom_mac_addr_base);
233#endif
234
235#ifndef CONFIG_MIPS64
236 debug_vectors->printf("Booting Linux kernel...\n");
237#endif
238}
239
240unsigned long __init prom_free_prom_memory(void)
241{
242 return 0;
243}
diff --git a/arch/mips/momentum/ocelot_c/reset.c b/arch/mips/momentum/ocelot_c/reset.c
new file mode 100644
index 000000000000..1f2b4263cc8c
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/reset.c
@@ -0,0 +1,59 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 * Copyright (C) 2002 Momentum Computer Inc.
12 * Author: Matthew Dharm <mdharm@momenco.com>
13 *
14 * Louis Hamilton, Red Hat, Inc.
15 * hamilton@redhat.com [MIPS64 modifications]
16 */
17#include <linux/config.h>
18#include <linux/sched.h>
19#include <linux/mm.h>
20#include <asm/io.h>
21#include <asm/pgtable.h>
22#include <asm/processor.h>
23#include <asm/reboot.h>
24#include <asm/system.h>
25#include <linux/delay.h>
26
27void momenco_ocelot_restart(char *command)
28{
29 /* base address of timekeeper portion of part */
30 void *nvram = (void *)
31#ifdef CONFIG_MIPS64
32 0xfffffffffc807000;
33#else
34 0xfc807000;
35#endif
36
37 /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
38 writeb(0x84, nvram + 0xff7);
39
40 /* wait for the watchdog to go off */
41 mdelay(100+(1000/16));
42
43 /* if the watchdog fails for some reason, let people know */
44 printk(KERN_NOTICE "Watchdog reset failed\n");
45}
46
47void momenco_ocelot_halt(void)
48{
49 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
50 while (1)
51 __asm__(".set\tmips3\n\t"
52 "wait\n\t"
53 ".set\tmips0");
54}
55
56void momenco_ocelot_power_off(void)
57{
58 momenco_ocelot_halt();
59}
diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c
new file mode 100644
index 000000000000..021c00e3c07c
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/setup.c
@@ -0,0 +1,363 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Ocelot-C and -CS board dependent boot routines
4 *
5 * Copyright (C) 1996, 1997, 2001 Ralf Baechle
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
9 *
10 * Author: Matthew Dharm, Momentum Computer
11 * mdharm@momenco.com
12 *
13 * Louis Hamilton, Red Hat, Inc.
14 * hamilton@redhat.com [MIPS64 modifications]
15 *
16 * Author: RidgeRun, Inc.
17 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
18 *
19 * Copyright 2001 MontaVista Software Inc.
20 * Author: jsun@mvista.com or jsun@junsun.net
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License as published by the
24 * Free Software Foundation; either version 2 of the License, or (at your
25 * option) any later version.
26 *
27 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
30 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
33 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * You should have received a copy of the GNU General Public License along
39 * with this program; if not, write to the Free Software Foundation, Inc.,
40 * 675 Mass Ave, Cambridge, MA 02139, USA.
41 *
42 */
43#include <linux/config.h>
44#include <linux/bcd.h>
45#include <linux/init.h>
46#include <linux/kernel.h>
47#include <linux/types.h>
48#include <linux/mm.h>
49#include <linux/swap.h>
50#include <linux/ioport.h>
51#include <linux/sched.h>
52#include <linux/interrupt.h>
53#include <linux/pci.h>
54#include <linux/timex.h>
55#include <linux/vmalloc.h>
56#include <asm/time.h>
57#include <asm/bootinfo.h>
58#include <asm/page.h>
59#include <asm/io.h>
60#include <asm/irq.h>
61#include <asm/pci.h>
62#include <asm/processor.h>
63#include <asm/ptrace.h>
64#include <asm/reboot.h>
65#include <linux/bootmem.h>
66#include <linux/blkdev.h>
67#include <asm/mv64340.h>
68#include "ocelot_c_fpga.h"
69
70unsigned long marvell_base;
71extern unsigned long mv64340_sram_base;
72unsigned long cpu_clock;
73
74/* These functions are used for rebooting or halting the machine*/
75extern void momenco_ocelot_restart(char *command);
76extern void momenco_ocelot_halt(void);
77extern void momenco_ocelot_power_off(void);
78
79void momenco_time_init(void);
80
81static char reset_reason;
82
83void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask);
84
85static unsigned long ENTRYLO(unsigned long paddr)
86{
87 return ((paddr & PAGE_MASK) |
88 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
89 _CACHE_UNCACHED)) >> 6;
90}
91
92/* setup code for a handoff from a version 2 PMON 2000 PROM */
93void PMON_v2_setup(void)
94{
95 /* Some wired TLB entries for the MV64340 and perhiperals. The
96 MV64340 is going to be hit on every IRQ anyway - there's
97 absolutely no point in letting it be a random TLB entry, as
98 it'll just cause needless churning of the TLB. And we use
99 the other half for the serial port, which is just a PITA
100 otherwise :)
101
102 Device Physical Virtual
103 MV64340 Internal Regs 0xf4000000 0xf4000000
104 Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
105 NVRAM (CS1) 0xfc800000 0xfc800000
106 UARTs (CS2) 0xfd000000 0xfd000000
107 Internal SRAM 0xfe000000 0xfe000000
108 M-Systems DOC (CS3) 0xff000000 0xff000000
109 */
110 printk("PMON_v2_setup\n");
111
112#ifdef CONFIG_MIPS64
113 /* marvell and extra space */
114 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K);
115 /* fpga, rtc, and uart */
116 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfffffffffc000000, PM_16M);
117 /* m-sys and internal SRAM */
118 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
119
120 marvell_base = 0xfffffffff4000000;
121 mv64340_sram_base = 0xfffffffffe000000;
122#else
123 /* marvell and extra space */
124 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
125 /* fpga, rtc, and uart */
126 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M);
127 /* m-sys and internal SRAM */
128 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
129
130 marvell_base = 0xf4000000;
131 mv64340_sram_base = 0xfe000000;
132#endif
133}
134
135unsigned long m48t37y_get_time(void)
136{
137#ifdef CONFIG_MIPS64
138 unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000;
139#else
140 unsigned char* rtc_base = (unsigned char*)0xfc800000;
141#endif
142 unsigned int year, month, day, hour, min, sec;
143
144 /* stop the update */
145 rtc_base[0x7ff8] = 0x40;
146
147 year = BCD2BIN(rtc_base[0x7fff]);
148 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
149
150 month = BCD2BIN(rtc_base[0x7ffe]);
151
152 day = BCD2BIN(rtc_base[0x7ffd]);
153
154 hour = BCD2BIN(rtc_base[0x7ffb]);
155 min = BCD2BIN(rtc_base[0x7ffa]);
156 sec = BCD2BIN(rtc_base[0x7ff9]);
157
158 /* start the update */
159 rtc_base[0x7ff8] = 0x00;
160
161 return mktime(year, month, day, hour, min, sec);
162}
163
164int m48t37y_set_time(unsigned long sec)
165{
166#ifdef CONFIG_MIPS64
167 unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000;
168#else
169 unsigned char* rtc_base = (unsigned char*)0xfc800000;
170#endif
171 struct rtc_time tm;
172
173 /* convert to a more useful format -- note months count from 0 */
174 to_tm(sec, &tm);
175 tm.tm_mon += 1;
176
177 /* enable writing */
178 rtc_base[0x7ff8] = 0x80;
179
180 /* year */
181 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
182 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
183
184 /* month */
185 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
186
187 /* day */
188 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
189
190 /* hour/min/sec */
191 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
192 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
193 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
194
195 /* day of week -- not really used, but let's keep it up-to-date */
196 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
197
198 /* disable writing */
199 rtc_base[0x7ff8] = 0x00;
200
201 return 0;
202}
203
204void momenco_timer_setup(struct irqaction *irq)
205{
206 setup_irq(7, irq);
207}
208
209void momenco_time_init(void)
210{
211#ifdef CONFIG_CPU_SR71000
212 mips_hpt_frequency = cpu_clock;
213#elif defined(CONFIG_CPU_RM7000)
214 mips_hpt_frequency = cpu_clock / 2;
215#else
216#error Unknown CPU for this board
217#endif
218 printk("momenco_time_init cpu_clock=%d\n", cpu_clock);
219 board_timer_setup = momenco_timer_setup;
220
221 rtc_get_time = m48t37y_get_time;
222 rtc_set_time = m48t37y_set_time;
223}
224
225static void __init momenco_ocelot_c_setup(void)
226{
227 unsigned int tmpword;
228
229 board_time_init = momenco_time_init;
230
231 _machine_restart = momenco_ocelot_restart;
232 _machine_halt = momenco_ocelot_halt;
233 _machine_power_off = momenco_ocelot_power_off;
234
235 /*
236 * initrd_start = (ulong)ocelot_initrd_start;
237 * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
238 * initrd_below_start_ok = 1;
239 */
240
241 /* do handoff reconfiguration */
242 PMON_v2_setup();
243
244 /* shut down ethernet ports, just to be sure our memory doesn't get
245 * corrupted by random ethernet traffic.
246 */
247 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
248 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
249 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
250 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
251 do {}
252 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
253 do {}
254 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
255 do {}
256 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
257 do {}
258 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
259 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
260 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
261 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
262 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
263
264 /* Turn off the Bit-Error LED */
265 OCELOT_FPGA_WRITE(0x80, CLR);
266
267 tmpword = OCELOT_FPGA_READ(BOARDREV);
268#ifdef CONFIG_CPU_SR71000
269 if (tmpword < 26)
270 printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n",
271 'A'+tmpword);
272 else
273 printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n",
274 tmpword);
275#else
276 if (tmpword < 26)
277 printk("Momenco Ocelot-C: Board Assembly Rev. %c\n",
278 'A'+tmpword);
279 else
280 printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n",
281 tmpword);
282#endif
283
284 tmpword = OCELOT_FPGA_READ(FPGA_REV);
285 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
286 tmpword = OCELOT_FPGA_READ(RESET_STATUS);
287 printk("Reset reason: 0x%x\n", tmpword);
288 switch (tmpword) {
289 case 0x1:
290 printk(" - Power-up reset\n");
291 break;
292 case 0x2:
293 printk(" - Push-button reset\n");
294 break;
295 case 0x4:
296 printk(" - cPCI bus reset\n");
297 break;
298 case 0x8:
299 printk(" - Watchdog reset\n");
300 break;
301 case 0x10:
302 printk(" - Software reset\n");
303 break;
304 default:
305 printk(" - Unknown reset cause\n");
306 }
307 reset_reason = tmpword;
308 OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
309
310 tmpword = OCELOT_FPGA_READ(CPCI_ID);
311 printk("cPCI ID register: 0x%02x\n", tmpword);
312 printk(" - Slot number: %d\n", tmpword & 0x1f);
313 printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
314 printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
315
316 tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
317 printk("Board Status register: 0x%02x\n", tmpword);
318 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
319 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
320 printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
321 printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
322
323 switch(tmpword &3) {
324 case 3:
325 /* 512MiB */
326 add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM);
327 break;
328 case 2:
329 /* 256MiB */
330 add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
331 break;
332 case 1:
333 /* 128MiB */
334 add_memory_region(0x0, 0x80<<20, BOOT_MEM_RAM);
335 break;
336 case 0:
337 /* 1GiB -- needs CONFIG_HIGHMEM */
338 add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM);
339 break;
340 }
341}
342
343early_initcall(momenco_ocelot_c_setup);
344
345#ifndef CONFIG_MIPS64
346/* This needs to be one of the first initcalls, because no I/O port access
347 can work before this */
348static int io_base_ioremap(void)
349{
350 /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
351 void *io_remap_range = ioremap(0xc0000000, 0x30000000);
352
353 if (!io_remap_range) {
354 panic("Could not ioremap I/O port range");
355 }
356 printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range);
357 set_io_port_base(io_remap_range - 0xc0000000);
358
359 return 0;
360}
361
362module_init(io_base_ioremap);
363#endif
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
new file mode 100644
index 000000000000..ebe1507b17df
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/uart-irq.c
@@ -0,0 +1,147 @@
1/*
2 * Copyright 2002 Momentum Computer
3 * Author: mdharm@momenco.com
4 *
5 * arch/mips/momentum/ocelot_c/uart-irq.c
6 * Interrupt routines for UARTs. Interrupt numbers are assigned from
7 * 80 to 81 (2 interrupt sources).
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/kernel.h>
19#include <asm/ptrace.h>
20#include <linux/sched.h>
21#include <linux/kernel_stat.h>
22#include <asm/io.h>
23#include <asm/irq.h>
24#include "ocelot_c_fpga.h"
25
26static inline int ls1bit8(unsigned int x)
27{
28 int b = 7, s;
29
30 s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
31 s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
32 s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
33
34 return b;
35}
36
37/* mask off an interrupt -- 0 is enable, 1 is disable */
38static inline void mask_uart_irq(unsigned int irq)
39{
40 uint8_t value;
41
42 value = OCELOT_FPGA_READ(UART_INTMASK);
43 value |= 1 << (irq - 74);
44 OCELOT_FPGA_WRITE(value, UART_INTMASK);
45
46 /* read the value back to assure that it's really been written */
47 value = OCELOT_FPGA_READ(UART_INTMASK);
48}
49
50/* unmask an interrupt -- 0 is enable, 1 is disable */
51static inline void unmask_uart_irq(unsigned int irq)
52{
53 uint8_t value;
54
55 value = OCELOT_FPGA_READ(UART_INTMASK);
56 value &= ~(1 << (irq - 74));
57 OCELOT_FPGA_WRITE(value, UART_INTMASK);
58
59 /* read the value back to assure that it's really been written */
60 value = OCELOT_FPGA_READ(UART_INTMASK);
61}
62
63/*
64 * Enables the IRQ in the FPGA
65 */
66static void enable_uart_irq(unsigned int irq)
67{
68 unmask_uart_irq(irq);
69}
70
71/*
72 * Initialize the IRQ in the FPGA
73 */
74static unsigned int startup_uart_irq(unsigned int irq)
75{
76 unmask_uart_irq(irq);
77 return 0;
78}
79
80/*
81 * Disables the IRQ in the FPGA
82 */
83static void disable_uart_irq(unsigned int irq)
84{
85 mask_uart_irq(irq);
86}
87
88/*
89 * Masks and ACKs an IRQ
90 */
91static void mask_and_ack_uart_irq(unsigned int irq)
92{
93 mask_uart_irq(irq);
94}
95
96/*
97 * End IRQ processing
98 */
99static void end_uart_irq(unsigned int irq)
100{
101 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
102 unmask_uart_irq(irq);
103}
104
105/*
106 * Interrupt handler for interrupts coming from the FPGA chip.
107 */
108void ll_uart_irq(struct pt_regs *regs)
109{
110 unsigned int irq_src, irq_mask;
111
112 /* read the interrupt status registers */
113 irq_src = OCELOT_FPGA_READ(UART_INTSTAT);
114 irq_mask = OCELOT_FPGA_READ(UART_INTMASK);
115
116 /* mask for just the interrupts we want */
117 irq_src &= ~irq_mask;
118
119 do_IRQ(ls1bit8(irq_src) + 74, regs);
120}
121
122#define shutdown_uart_irq disable_uart_irq
123
124struct hw_interrupt_type uart_irq_type = {
125 "UART/FPGA",
126 startup_uart_irq,
127 shutdown_uart_irq,
128 enable_uart_irq,
129 disable_uart_irq,
130 mask_and_ack_uart_irq,
131 end_uart_irq,
132 NULL
133};
134
135void uart_irq_init(void)
136{
137 /* Reset irq handlers pointers to NULL */
138 irq_desc[80].status = IRQ_DISABLED;
139 irq_desc[80].action = 0;
140 irq_desc[80].depth = 2;
141 irq_desc[80].handler = &uart_irq_type;
142
143 irq_desc[81].status = IRQ_DISABLED;
144 irq_desc[81].action = 0;
145 irq_desc[81].depth = 2;
146 irq_desc[81].handler = &uart_irq_type;
147}
diff --git a/arch/mips/momentum/ocelot_g/Makefile b/arch/mips/momentum/ocelot_g/Makefile
new file mode 100644
index 000000000000..e5f1cb086973
--- /dev/null
+++ b/arch/mips/momentum/ocelot_g/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for Momentum Computer's Ocelot-G board.
3#
4
5obj-y += int-handler.o irq.o gt-irq.o prom.o reset.o setup.o
6obj-$(CONFIG_KGDB) += dbg_io.o
7
8EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/momentum/ocelot_g/dbg_io.c b/arch/mips/momentum/ocelot_g/dbg_io.c
new file mode 100644
index 000000000000..8720bccfdea2
--- /dev/null
+++ b/arch/mips/momentum/ocelot_g/dbg_io.c
@@ -0,0 +1,126 @@
1#include <linux/config.h>
2
3#ifdef CONFIG_KGDB
4
5#include <asm/serial.h> /* For the serial port location and base baud */
6
7/* --- CONFIG --- */
8
9typedef unsigned char uint8;
10typedef unsigned int uint32;
11
12/* --- END OF CONFIG --- */
13
14#define UART16550_BAUD_2400 2400
15#define UART16550_BAUD_4800 4800
16#define UART16550_BAUD_9600 9600
17#define UART16550_BAUD_19200 19200
18#define UART16550_BAUD_38400 38400
19#define UART16550_BAUD_57600 57600
20#define UART16550_BAUD_115200 115200
21
22#define UART16550_PARITY_NONE 0
23#define UART16550_PARITY_ODD 0x08
24#define UART16550_PARITY_EVEN 0x18
25#define UART16550_PARITY_MARK 0x28
26#define UART16550_PARITY_SPACE 0x38
27
28#define UART16550_DATA_5BIT 0x0
29#define UART16550_DATA_6BIT 0x1
30#define UART16550_DATA_7BIT 0x2
31#define UART16550_DATA_8BIT 0x3
32
33#define UART16550_STOP_1BIT 0x0
34#define UART16550_STOP_2BIT 0x4
35
36/* ----------------------------------------------------- */
37
38/* === CONFIG === */
39
40/* [jsun] we use the second serial port for kdb */
41#define BASE OCELOT_SERIAL1_BASE
42#define MAX_BAUD OCELOT_BASE_BAUD
43
44/* === END OF CONFIG === */
45
46#define REG_OFFSET 4
47
48/* register offset */
49#define OFS_RCV_BUFFER 0
50#define OFS_TRANS_HOLD 0
51#define OFS_SEND_BUFFER 0
52#define OFS_INTR_ENABLE (1*REG_OFFSET)
53#define OFS_INTR_ID (2*REG_OFFSET)
54#define OFS_DATA_FORMAT (3*REG_OFFSET)
55#define OFS_LINE_CONTROL (3*REG_OFFSET)
56#define OFS_MODEM_CONTROL (4*REG_OFFSET)
57#define OFS_RS232_OUTPUT (4*REG_OFFSET)
58#define OFS_LINE_STATUS (5*REG_OFFSET)
59#define OFS_MODEM_STATUS (6*REG_OFFSET)
60#define OFS_RS232_INPUT (6*REG_OFFSET)
61#define OFS_SCRATCH_PAD (7*REG_OFFSET)
62
63#define OFS_DIVISOR_LSB (0*REG_OFFSET)
64#define OFS_DIVISOR_MSB (1*REG_OFFSET)
65
66
67/* memory-mapped read/write of the port */
68#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
69#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
70
71void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
72{
73 /* disable interrupts */
74 UART16550_WRITE(OFS_INTR_ENABLE, 0);
75
76 /* set up buad rate */
77 {
78 uint32 divisor;
79
80 /* set DIAB bit */
81 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
82
83 /* set divisor */
84 divisor = MAX_BAUD / baud;
85 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
86 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
87
88 /* clear DIAB bit */
89 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
90 }
91
92 /* set data format */
93 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
94}
95
96static int remoteDebugInitialized = 0;
97
98uint8 getDebugChar(void)
99{
100 if (!remoteDebugInitialized) {
101 remoteDebugInitialized = 1;
102 debugInit(UART16550_BAUD_38400,
103 UART16550_DATA_8BIT,
104 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
105 }
106
107 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
108 return UART16550_READ(OFS_RCV_BUFFER);
109}
110
111
112int putDebugChar(uint8 byte)
113{
114 if (!remoteDebugInitialized) {
115 remoteDebugInitialized = 1;
116 debugInit(UART16550_BAUD_38400,
117 UART16550_DATA_8BIT,
118 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
119 }
120
121 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
122 UART16550_WRITE(OFS_SEND_BUFFER, byte);
123 return 1;
124}
125
126#endif
diff --git a/arch/mips/momentum/ocelot_g/gt-irq.c b/arch/mips/momentum/ocelot_g/gt-irq.c
new file mode 100644
index 000000000000..d0b5c9dd0ea4
--- /dev/null
+++ b/arch/mips/momentum/ocelot_g/gt-irq.c
@@ -0,0 +1,214 @@
1/*
2 *
3 * Copyright 2002 Momentum Computer
4 * Author: mdharm@momenco.com
5 *
6 * arch/mips/momentum/ocelot_g/gt_irq.c
7 * Interrupt routines for gt64240. Currently it only handles timer irq.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/config.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/kernel.h>
18#include <asm/ptrace.h>
19#include <linux/sched.h>
20#include <linux/kernel_stat.h>
21#include <asm/gt64240.h>
22#include <asm/io.h>
23
24unsigned long bus_clock;
25
26/*
27 * These are interrupt handlers for the GT on-chip interrupts. They
28 * all come in to the MIPS on a single interrupt line, and have to
29 * be handled and ack'ed differently than other MIPS interrupts.
30 */
31
32#if CURRENTLY_UNUSED
33
34struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];
35void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr);
36
37/*
38 * Hooks IRQ handler to the system. When the system is interrupted
39 * the interrupt service routine is called.
40 *
41 * Inputs :
42 * int_cause - The interrupt cause number. In EVB64120 two parameters
43 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
44 * bit_num - Indicates which bit number in the cause register
45 * isr_ptr - Pointer to the interrupt service routine
46 */
47void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr)
48{
49 irq_handlers[int_cause][bit_num].routine = isr_ptr;
50}
51
52
53/*
54 * Enables the IRQ on Galileo Chip
55 *
56 * Inputs :
57 * int_cause - The interrupt cause number. In EVB64120 two parameters
58 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
59 * bit_num - Indicates which bit number in the cause register
60 *
61 * Outputs :
62 * 1 if succesful, 0 if failure
63 */
64int enable_galileo_irq(int int_cause, int bit_num)
65{
66 if (int_cause == INT_CAUSE_MAIN)
67 SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num));
68 else if (int_cause == INT_CAUSE_HIGH)
69 SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
70 (1 << bit_num));
71 else
72 return 0;
73
74 return 1;
75}
76
77/*
78 * Disables the IRQ on Galileo Chip
79 *
80 * Inputs :
81 * int_cause - The interrupt cause number. In EVB64120 two parameters
82 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
83 * bit_num - Indicates which bit number in the cause register
84 *
85 * Outputs :
86 * 1 if succesful, 0 if failure
87 */
88int disable_galileo_irq(int int_cause, int bit_num)
89{
90 if (int_cause == INT_CAUSE_MAIN)
91 RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER,
92 (1 << bit_num));
93 else if (int_cause == INT_CAUSE_HIGH)
94 RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
95 (1 << bit_num));
96 else
97 return 0;
98 return 1;
99}
100#endif /* UNUSED */
101
102/*
103 * Interrupt handler for interrupts coming from the Galileo chip via P0_INT#.
104 *
105 * We route the timer interrupt to P0_INT# (IRQ 6), and that's all this
106 * routine can handle, for now.
107 *
108 * In the future, we'll route more interrupts to this pin, and that's why
109 * we keep this particular structure in the function.
110 */
111
112static irqreturn_t gt64240_p0int_irq(int irq, void *dev, struct pt_regs *regs)
113{
114 uint32_t irq_src, irq_src_mask;
115 int handled;
116
117 /* get the low interrupt cause register */
118 irq_src = MV_READ(LOW_INTERRUPT_CAUSE_REGISTER);
119
120 /* get the mask register for this pin */
121 irq_src_mask = MV_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW);
122
123 /* mask off only the interrupts we're interested in */
124 irq_src = irq_src & irq_src_mask;
125
126 handled = IRQ_NONE;
127
128 /* Check for timer interrupt */
129 if (irq_src & 0x00000100) {
130 handled = IRQ_HANDLED;
131 irq_src &= ~0x00000100;
132
133 /* Clear any pending cause bits */
134 MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
135
136 /* handle the timer call */
137 do_timer(regs);
138#ifndef CONFIG_SMP
139 update_process_times(user_mode(regs));
140#endif
141 }
142
143 if (irq_src) {
144 printk(KERN_INFO
145 "UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n",
146 irq_src);
147 }
148
149 return handled;
150}
151
152/*
153 * Initializes timer using galileo's built in timer.
154 */
155
156/*
157 * This will ignore the standard MIPS timer interrupt handler
158 * that is passed in as *irq (=irq0 in ../kernel/time.c).
159 * We will do our own timer interrupt handling.
160 */
161void gt64240_time_init(void)
162{
163 static struct irqaction timer;
164
165 /* Stop the timer -- we'll use timer #0 */
166 MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0);
167
168 /* Load timer value for 100 Hz */
169 MV_WRITE(TIMER_COUNTER0, bus_clock / 100);
170
171 /*
172 * Create the IRQ structure entry for the timer. Since we're too early
173 * in the boot process to use the "request_irq()" call, we'll hard-code
174 * the values to the correct interrupt line.
175 */
176 timer.handler = &gt64240_p0int_irq;
177 timer.flags = SA_SHIRQ | SA_INTERRUPT;
178 timer.name = "timer";
179 timer.dev_id = NULL;
180 timer.next = NULL;
181 timer.mask = 0;
182 irq_desc[6].action = &timer;
183
184 enable_irq(6);
185
186 /* Clear any pending cause bits */
187 MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
188
189 /* Enable the interrupt for timer 0 */
190 MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1);
191
192 /* Enable the timer interrupt for GT-64240 pin P0_INT# */
193 MV_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100);
194
195 /* Configure and start the timer */
196 MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3);
197}
198
199void gt64240_irq_init(void)
200{
201#if CURRENTLY_UNUSED
202 int i, j;
203
204 /* Reset irq handlers pointers to NULL */
205 for (i = 0; i < MAX_CAUSE_REGS; i++) {
206 for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) {
207 irq_handlers[i][j].next = NULL;
208 irq_handlers[i][j].sync = 0;
209 irq_handlers[i][j].routine = NULL;
210 irq_handlers[i][j].data = NULL;
211 }
212 }
213#endif
214}
diff --git a/arch/mips/momentum/ocelot_g/int-handler.S b/arch/mips/momentum/ocelot_g/int-handler.S
new file mode 100644
index 000000000000..772e8f713176
--- /dev/null
+++ b/arch/mips/momentum/ocelot_g/int-handler.S
@@ -0,0 +1,131 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * First-level interrupt dispatcher for ocelot board.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12#include <asm/asm.h>
13#include <asm/mipsregs.h>
14#include <asm/addrspace.h>
15#include <asm/regdef.h>
16#include <asm/stackframe.h>
17
18/*
19 * first level interrupt dispatcher for ocelot board -
20 * We check for the timer first, then check PCI ints A and D.
21 * Then check for serial IRQ and fall through.
22 */
23 .align 5
24 NESTED(ocelot_handle_int, PT_SIZE, sp)
25 SAVE_ALL
26 CLI
27 .set at
28 mfc0 t0, CP0_CAUSE
29 mfc0 t2, CP0_STATUS
30
31 and t0, t2
32
33 andi t1, t0, STATUSF_IP2 /* int0 hardware line */
34 bnez t1, ll_pri_enet_irq
35 andi t1, t0, STATUSF_IP3 /* int1 hardware line */
36 bnez t1, ll_sec_enet_irq
37 andi t1, t0, STATUSF_IP4 /* int2 hardware line */
38 bnez t1, ll_uart_irq
39 andi t1, t0, STATUSF_IP5 /* int3 hardware line */
40 bnez t1, ll_cpci_irq
41 andi t1, t0, STATUSF_IP6 /* int4 hardware line */
42 bnez t1, ll_galileo_p0_irq
43 andi t1, t0, STATUSF_IP7 /* cpu timer */
44 bnez t1, ll_cputimer_irq
45
46 /* now look at the extended interrupts */
47 mfc0 t0, CP0_CAUSE
48 cfc0 t1, CP0_S1_INTCONTROL
49
50 /* shift the mask 8 bits left to line up the bits */
51 sll t2, t1, 8
52
53 and t0, t2
54 srl t0, t0, 16
55
56 andi t1, t0, STATUSF_IP8 /* int6 hardware line */
57 bnez t1, ll_galileo_p1_irq
58 andi t1, t0, STATUSF_IP9 /* int7 hardware line */
59 bnez t1, ll_pmc_irq
60 andi t1, t0, STATUSF_IP10 /* int8 hardware line */
61 bnez t1, ll_cpci_abcd_irq
62 andi t1, t0, STATUSF_IP11 /* int9 hardware line */
63 bnez t1, ll_testpoint_irq
64
65 .set reorder
66
67 /* wrong alarm or masked ... */
68 j spurious_interrupt
69 nop
70 END(ocelot_handle_int)
71
72 .align 5
73ll_pri_enet_irq:
74 li a0, 2
75 move a1, sp
76 jal do_IRQ
77 j ret_from_irq
78
79ll_sec_enet_irq:
80 li a0, 3
81 move a1, sp
82 jal do_IRQ
83 j ret_from_irq
84
85ll_uart_irq:
86 li a0, 4
87 move a1, sp
88 jal do_IRQ
89 j ret_from_irq
90
91ll_cpci_irq:
92 li a0, 5
93 move a1, sp
94 jal do_IRQ
95 j ret_from_irq
96
97ll_galileo_p0_irq:
98 li a0, 6
99 move a1, sp
100 jal do_IRQ
101 j ret_from_irq
102
103ll_cputimer_irq:
104 li a0, 7
105 move a1, sp
106 jal do_IRQ
107 j ret_from_irq
108
109ll_galileo_p1_irq:
110 li a0, 8
111 move a1, sp
112 jal do_IRQ
113 j ret_from_irq
114
115ll_pmc_irq:
116 li a0, 9
117 move a1, sp
118 jal do_IRQ
119 j ret_from_irq
120
121ll_cpci_abcd_irq:
122 li a0, 10
123 move a1, sp
124 jal do_IRQ
125 j ret_from_irq
126
127ll_testpoint_irq:
128 li a0, 11
129 move a1, sp
130 jal do_IRQ
131 j ret_from_irq
diff --git a/arch/mips/momentum/ocelot_g/irq.c b/arch/mips/momentum/ocelot_g/irq.c
new file mode 100644
index 000000000000..5eb85b164205
--- /dev/null
+++ b/arch/mips/momentum/ocelot_g/irq.c
@@ -0,0 +1,69 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 *
30 */
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/kernel_stat.h>
34#include <linux/module.h>
35#include <linux/signal.h>
36#include <linux/sched.h>
37#include <linux/types.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/timex.h>
41#include <linux/slab.h>
42#include <linux/random.h>
43#include <linux/bitops.h>
44#include <asm/bootinfo.h>
45#include <asm/io.h>
46#include <asm/irq.h>
47#include <asm/irq_cpu.h>
48#include <asm/mipsregs.h>
49#include <asm/system.h>
50
51extern asmlinkage void ocelot_handle_int(void);
52extern void gt64240_irq_init(void);
53
54void __init arch_init_irq(void)
55{
56 /*
57 * Clear all of the interrupts while we change the able around a bit.
58 * int-handler is not on bootstrap
59 */
60 clear_c0_status(ST0_IM);
61 local_irq_disable();
62
63 /* Sets the first-level interrupt dispatcher. */
64 set_except_vector(0, ocelot_handle_int);
65 mips_cpu_irq_init(0);
66 rm7k_cpu_irq_init(8);
67
68 gt64240_irq_init();
69}
diff --git a/arch/mips/momentum/ocelot_g/ocelot_pld.h b/arch/mips/momentum/ocelot_g/ocelot_pld.h
new file mode 100644
index 000000000000..fcb8275e219d
--- /dev/null
+++ b/arch/mips/momentum/ocelot_g/ocelot_pld.h
@@ -0,0 +1,30 @@
1/*
2 * Ocelot Board Register Definitions
3 *
4 * (C) 2001 Red Hat, Inc.
5 *
6 * GPL'd
7 */
8#ifndef __MOMENCO_OCELOT_PLD_H__
9#define __MOMENCO_OCELOT_PLD_H__
10
11#define OCELOT_CS0_ADDR (0xfc000000)
12
13#define OCELOT_REG_BOARDREV (0)
14#define OCELOT_REG_PLD1_ID (1)
15#define OCELOT_REG_PLD2_ID (2)
16#define OCELOT_REG_RESET_STATUS (3)
17#define OCELOT_REG_BOARD_STATUS (4)
18#define OCELOT_REG_CPCI_ID (5)
19#define OCELOT_REG_I2C_CTRL (8)
20#define OCELOT_REG_EEPROM_MODE (9)
21#define OCELOT_REG_INTMASK (10)
22#define OCELOT_REG_INTSTATUS (11)
23#define OCELOT_REG_INTSET (12)
24#define OCELOT_REG_INTCLR (13)
25
26#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y)
27#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x)
28
29
30#endif /* __MOMENCO_OCELOT_PLD_H__ */
diff --git a/arch/mips/momentum/ocelot_g/prom.c b/arch/mips/momentum/ocelot_g/prom.c
new file mode 100644
index 000000000000..6b4f577c2757
--- /dev/null
+++ b/arch/mips/momentum/ocelot_g/prom.c
@@ -0,0 +1,86 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on Ocelot Linux port, which is
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: jsun@mvista.com or jsun@junsun.net
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/sched.h>
18#include <linux/bootmem.h>
19
20#include <asm/addrspace.h>
21#include <asm/bootinfo.h>
22#include <asm/pmon.h>
23#include <asm/gt64240.h>
24
25#include "ocelot_pld.h"
26
27struct callvectors* debug_vectors;
28
29extern unsigned long marvell_base;
30extern unsigned long bus_clock;
31
32#ifdef CONFIG_GALILLEO_GT64240_ETH
33extern unsigned char prom_mac_addr_base[6];
34#endif
35
36const char *get_system_type(void)
37{
38 return "Momentum Ocelot";
39}
40
41void __init prom_init(void)
42{
43 int argc = fw_arg0;
44 char **arg = (char **) fw_arg1;
45 char **env = (char **) fw_arg2;
46 struct callvectors *cv = (struct callvectors *) fw_arg3;
47 int i;
48
49 /* save the PROM vectors for debugging use */
50 debug_vectors = cv;
51
52 /* arg[0] is "g", the rest is boot parameters */
53 arcs_cmdline[0] = '\0';
54 for (i = 1; i < argc; i++) {
55 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
56 >= sizeof(arcs_cmdline))
57 break;
58 strcat(arcs_cmdline, arg[i]);
59 strcat(arcs_cmdline, " ");
60 }
61
62 mips_machgroup = MACH_GROUP_MOMENCO;
63 mips_machtype = MACH_MOMENCO_OCELOT_G;
64
65#ifdef CONFIG_GALILLEO_GT64240_ETH
66 /* get the base MAC address for on-board ethernet ports */
67 memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6);
68#endif
69
70 while (*env) {
71 if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
72 marvell_base = simple_strtol(*env + strlen("gtbase="),
73 NULL, 16);
74 }
75 if (strncmp("busclock", *env, strlen("busclock")) == 0) {
76 bus_clock = simple_strtol(*env + strlen("busclock="),
77 NULL, 10);
78 }
79 env++;
80 }
81}
82
83unsigned long __init prom_free_prom_memory(void)
84{
85 return 0;
86}
diff --git a/arch/mips/momentum/ocelot_g/reset.c b/arch/mips/momentum/ocelot_g/reset.c
new file mode 100644
index 000000000000..3fd499adf4cf
--- /dev/null
+++ b/arch/mips/momentum/ocelot_g/reset.c
@@ -0,0 +1,47 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 */
11#include <linux/sched.h>
12#include <linux/mm.h>
13#include <asm/io.h>
14#include <asm/pgtable.h>
15#include <asm/processor.h>
16#include <asm/reboot.h>
17#include <asm/system.h>
18#include <linux/delay.h>
19
20void momenco_ocelot_restart(char *command)
21{
22 void *nvram = ioremap_nocache(0x2c807000, 0x1000);
23
24 if (!nvram) {
25 printk(KERN_NOTICE "ioremap of reset register failed\n");
26 return;
27 }
28 writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to
29 assert reset in 1/16 second */
30 mdelay(10+(1000/16));
31 iounmap(nvram);
32 printk(KERN_NOTICE "Watchdog reset failed\n");
33}
34
35void momenco_ocelot_halt(void)
36{
37 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
38 while (1)
39 __asm__(".set\tmips3\n\t"
40 "wait\n\t"
41 ".set\tmips0");
42}
43
44void momenco_ocelot_power_off(void)
45{
46 momenco_ocelot_halt();
47}
diff --git a/arch/mips/momentum/ocelot_g/setup.c b/arch/mips/momentum/ocelot_g/setup.c
new file mode 100644
index 000000000000..38a78ab8c830
--- /dev/null
+++ b/arch/mips/momentum/ocelot_g/setup.c
@@ -0,0 +1,266 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Ocelot-G (CP7000G) - board dependent boot routines
4 *
5 * Copyright (C) 1996, 1997, 2001 Ralf Baechle
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
9 *
10 * Author: Matthew Dharm, Momentum Computer
11 * mdharm@momenco.com
12 *
13 * Author: RidgeRun, Inc.
14 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
15 *
16 * Copyright 2001 MontaVista Software Inc.
17 * Author: jsun@mvista.com or jsun@junsun.net
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
23 *
24 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
27 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
30 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * You should have received a copy of the GNU General Public License along
36 * with this program; if not, write to the Free Software Foundation, Inc.,
37 * 675 Mass Ave, Cambridge, MA 02139, USA.
38 *
39 */
40#include <linux/config.h>
41#include <linux/init.h>
42#include <linux/kernel.h>
43#include <linux/types.h>
44#include <linux/mm.h>
45#include <linux/swap.h>
46#include <linux/ioport.h>
47#include <linux/sched.h>
48#include <linux/interrupt.h>
49#include <linux/pci.h>
50#include <linux/timex.h>
51#include <linux/vmalloc.h>
52#include <asm/time.h>
53#include <asm/bootinfo.h>
54#include <asm/page.h>
55#include <asm/io.h>
56#include <asm/gt64240.h>
57#include <asm/irq.h>
58#include <asm/pci.h>
59#include <asm/processor.h>
60#include <asm/ptrace.h>
61#include <asm/reboot.h>
62#include <linux/bootmem.h>
63
64#include "ocelot_pld.h"
65
66#ifdef CONFIG_GALILLEO_GT64240_ETH
67extern unsigned char prom_mac_addr_base[6];
68#endif
69
70unsigned long marvell_base;
71
72/* These functions are used for rebooting or halting the machine*/
73extern void momenco_ocelot_restart(char *command);
74extern void momenco_ocelot_halt(void);
75extern void momenco_ocelot_power_off(void);
76
77extern void gt64240_time_init(void);
78extern void momenco_ocelot_irq_setup(void);
79
80static char reset_reason;
81
82static unsigned long ENTRYLO(unsigned long paddr)
83{
84 return ((paddr & PAGE_MASK) |
85 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
86 _CACHE_UNCACHED)) >> 6;
87}
88
89/* setup code for a handoff from a version 2 PMON 2000 PROM */
90void PMON_v2_setup(void)
91{
92 /* A wired TLB entry for the GT64240 and the serial port. The
93 GT64240 is going to be hit on every IRQ anyway - there's
94 absolutely no point in letting it be a random TLB entry, as
95 it'll just cause needless churning of the TLB. And we use
96 the other half for the serial port, which is just a PITA
97 otherwise :)
98
99 Device Physical Virtual
100 GT64240 Internal Regs 0xf4000000 0xe0000000
101 UARTs (CS2) 0xfd000000 0xe0001000
102 */
103 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
104 0xf4000000, PM_64K);
105 add_wired_entry(ENTRYLO(0xfd000000), ENTRYLO(0xfd001000),
106 0xfd000000, PM_4K);
107
108 /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
109 in the CS[012] region. We can't use ioremap() yet. The NVRAM
110 is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
111
112 Ocelot PLD (CS0) 0xfc000000 0xe0020000
113 NVRAM (CS1) 0xfc800000 0xe0030000
114 */
115 add_temporary_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfc010000),
116 0xfc000000, PM_64K);
117 add_temporary_entry(ENTRYLO(0xfc800000), ENTRYLO(0xfc810000),
118 0xfc800000, PM_64K);
119
120 marvell_base = 0xf4000000;
121}
122
123extern int rm7k_tcache_enabled;
124
125/*
126 * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
127 */
128#define Page_Invalidate_T 0x16
129static void __init setup_l3cache(unsigned long size)
130{
131 int register i;
132
133 printk("Enabling L3 cache...");
134
135 /* Enable the L3 cache in the GT64120A's CPU Configuration register */
136 MV_WRITE(0, MV_READ(0) | (1<<14));
137
138 /* Enable the L3 cache in the CPU */
139 set_c0_config(1<<12 /* CONF_TE */);
140
141 /* Clear the cache */
142 write_c0_taglo(0);
143 write_c0_taghi(0);
144
145 for (i=0; i < size; i+= 4096) {
146 __asm__ __volatile__ (
147 ".set noreorder\n\t"
148 ".set mips3\n\t"
149 "cache %1, (%0)\n\t"
150 ".set mips0\n\t"
151 ".set reorder"
152 :
153 : "r" (KSEG0ADDR(i)),
154 "i" (Page_Invalidate_T));
155 }
156
157 /* Let the RM7000 MM code know that the tertiary cache is enabled */
158 rm7k_tcache_enabled = 1;
159
160 printk("Done\n");
161}
162
163static int __init momenco_ocelot_g_setup(void)
164{
165 void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache);
166 unsigned int tmpword;
167
168 board_time_init = gt64240_time_init;
169
170 _machine_restart = momenco_ocelot_restart;
171 _machine_halt = momenco_ocelot_halt;
172 _machine_power_off = momenco_ocelot_power_off;
173
174 /*
175 * initrd_start = (ulong)ocelot_initrd_start;
176 * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
177 * initrd_below_start_ok = 1;
178 */
179
180 /* do handoff reconfiguration */
181 PMON_v2_setup();
182
183#ifdef CONFIG_GALILLEO_GT64240_ETH
184 /* get the mac addr */
185 memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6);
186#endif
187
188 /* Turn off the Bit-Error LED */
189 OCELOT_PLD_WRITE(0x80, INTCLR);
190
191 tmpword = OCELOT_PLD_READ(BOARDREV);
192 if (tmpword < 26)
193 printk("Momenco Ocelot-G: Board Assembly Rev. %c\n", 'A'+tmpword);
194 else
195 printk("Momenco Ocelot-G: Board Assembly Revision #0x%x\n", tmpword);
196
197 tmpword = OCELOT_PLD_READ(PLD1_ID);
198 printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
199 tmpword = OCELOT_PLD_READ(PLD2_ID);
200 printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
201 tmpword = OCELOT_PLD_READ(RESET_STATUS);
202 printk("Reset reason: 0x%x\n", tmpword);
203 reset_reason = tmpword;
204 OCELOT_PLD_WRITE(0xff, RESET_STATUS);
205
206 tmpword = OCELOT_PLD_READ(BOARD_STATUS);
207 printk("Board Status register: 0x%02x\n", tmpword);
208 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
209 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
210 printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
211 printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
212 printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
213
214 if (tmpword&12)
215 l3func((1<<(((tmpword&12) >> 2)+20)));
216
217 switch(tmpword &3) {
218 case 3:
219 /* 512MiB -- two banks of 256MiB */
220 add_memory_region( 0x0<<20, 0x100<<20, BOOT_MEM_RAM);
221/*
222 add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
223*/
224 break;
225 case 2:
226 /* 256MiB -- two banks of 128MiB */
227 add_memory_region( 0x0<<20, 0x80<<20, BOOT_MEM_RAM);
228 add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
229 break;
230 case 1:
231 /* 128MiB -- 64MiB per bank */
232 add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
233 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
234 break;
235 case 0:
236 /* 64MiB */
237 add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
238 break;
239 }
240
241 /* FIXME: Fix up the DiskOnChip mapping */
242 MV_WRITE(0x468, 0xfef73);
243
244 return 0;
245}
246
247early_initcall(momenco_ocelot_g_setup);
248
249/* This needs to be one of the first initcalls, because no I/O port access
250 can work before this */
251
252static int io_base_ioremap(void)
253{
254 /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
255 unsigned long io_remap_range;
256
257 io_remap_range = (unsigned long) ioremap(0xc0000000, 0x30000000);
258 if (!io_remap_range)
259 panic("Could not ioremap I/O port range");
260
261 set_io_port_base(io_remap_range - 0xc0000000);
262
263 return 0;
264}
265
266module_init(io_base_ioremap);
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