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authorFranck Bui-Huu <vagabon.xyz@gmail.com>2007-06-11 09:08:55 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-07-10 12:33:01 -0400
commit192cca6ef2c49ac5ff46f7a31cb9dd175995658e (patch)
tree7df5158d92d5afe078aab30dd9cf152d828eac02 /arch/mips/momentum
parentcfd2afc0f654e86e3f0b5060409b90f21964b9d3 (diff)
[MIPS] Remove Momenco Ocelot C support
Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/configs/ocelot_c_defconfig delete mode 100644 arch/mips/momentum/ocelot_c/Makefile delete mode 100644 arch/mips/momentum/ocelot_c/cpci-irq.c delete mode 100644 arch/mips/momentum/ocelot_c/dbg_io.c delete mode 100644 arch/mips/momentum/ocelot_c/irq.c delete mode 100644 arch/mips/momentum/ocelot_c/ocelot_c_fpga.h delete mode 100644 arch/mips/momentum/ocelot_c/platform.c delete mode 100644 arch/mips/momentum/ocelot_c/prom.c delete mode 100644 arch/mips/momentum/ocelot_c/reset.c delete mode 100644 arch/mips/momentum/ocelot_c/setup.c delete mode 100644 arch/mips/momentum/ocelot_c/uart-irq.c delete mode 100644 arch/mips/pci/fixup-ocelot-c.c delete mode 100644 arch/mips/pci/pci-ocelot-c.c
Diffstat (limited to 'arch/mips/momentum')
-rw-r--r--arch/mips/momentum/ocelot_c/Makefile8
-rw-r--r--arch/mips/momentum/ocelot_c/cpci-irq.c100
-rw-r--r--arch/mips/momentum/ocelot_c/dbg_io.c121
-rw-r--r--arch/mips/momentum/ocelot_c/irq.c107
-rw-r--r--arch/mips/momentum/ocelot_c/ocelot_c_fpga.h61
-rw-r--r--arch/mips/momentum/ocelot_c/platform.c183
-rw-r--r--arch/mips/momentum/ocelot_c/prom.c183
-rw-r--r--arch/mips/momentum/ocelot_c/reset.c58
-rw-r--r--arch/mips/momentum/ocelot_c/setup.c362
-rw-r--r--arch/mips/momentum/ocelot_c/uart-irq.c91
10 files changed, 0 insertions, 1274 deletions
diff --git a/arch/mips/momentum/ocelot_c/Makefile b/arch/mips/momentum/ocelot_c/Makefile
deleted file mode 100644
index d69161aa1675..000000000000
--- a/arch/mips/momentum/ocelot_c/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for Momentum Computer's Ocelot-C and -CS boards.
3#
4
5obj-y += cpci-irq.o irq.o platform.o prom.o reset.o \
6 setup.o uart-irq.o
7
8obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
deleted file mode 100644
index 186a140fd2a9..000000000000
--- a/arch/mips/momentum/ocelot_c/cpci-irq.c
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * Copyright 2002 Momentum Computer
3 * Author: mdharm@momenco.com
4 *
5 * arch/mips/momentum/ocelot_c/cpci-irq.c
6 * Interrupt routines for cpci. Interrupt numbers are assigned from
7 * CPCI_IRQ_BASE to CPCI_IRQ_BASE+8 (8 interrupt sources).
8 *
9 * Note that the high-level software will need to be careful about using
10 * these interrupts. If this board is asserting a cPCI interrupt, it will
11 * also see the asserted interrupt. Care must be taken to avoid an
12 * interrupt flood.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19
20#include <linux/module.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/kernel.h>
24#include <linux/sched.h>
25#include <linux/kernel_stat.h>
26#include <asm/io.h>
27#include "ocelot_c_fpga.h"
28
29#define CPCI_IRQ_BASE 8
30
31static inline int ls1bit8(unsigned int x)
32{
33 int b = 7, s;
34
35 s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
36 s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
37 s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
38
39 return b;
40}
41
42/* mask off an interrupt -- 0 is enable, 1 is disable */
43static inline void mask_cpci_irq(unsigned int irq)
44{
45 uint32_t value;
46
47 value = OCELOT_FPGA_READ(INTMASK);
48 value |= 1 << (irq - CPCI_IRQ_BASE);
49 OCELOT_FPGA_WRITE(value, INTMASK);
50
51 /* read the value back to assure that it's really been written */
52 value = OCELOT_FPGA_READ(INTMASK);
53}
54
55/* unmask an interrupt -- 0 is enable, 1 is disable */
56static inline void unmask_cpci_irq(unsigned int irq)
57{
58 uint32_t value;
59
60 value = OCELOT_FPGA_READ(INTMASK);
61 value &= ~(1 << (irq - CPCI_IRQ_BASE));
62 OCELOT_FPGA_WRITE(value, INTMASK);
63
64 /* read the value back to assure that it's really been written */
65 value = OCELOT_FPGA_READ(INTMASK);
66}
67
68/*
69 * Interrupt handler for interrupts coming from the FPGA chip.
70 * It could be built in ethernet ports etc...
71 */
72void ll_cpci_irq(void)
73{
74 unsigned int irq_src, irq_mask;
75
76 /* read the interrupt status registers */
77 irq_src = OCELOT_FPGA_READ(INTSTAT);
78 irq_mask = OCELOT_FPGA_READ(INTMASK);
79
80 /* mask for just the interrupts we want */
81 irq_src &= ~irq_mask;
82
83 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE);
84}
85
86struct irq_chip cpci_irq_type = {
87 .name = "CPCI/FPGA",
88 .ack = mask_cpci_irq,
89 .mask = mask_cpci_irq,
90 .mask_ack = mask_cpci_irq,
91 .unmask = unmask_cpci_irq,
92};
93
94void cpci_irq_init(void)
95{
96 int i;
97
98 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++)
99 set_irq_chip_and_handler(i, &cpci_irq_type, handle_level_irq);
100}
diff --git a/arch/mips/momentum/ocelot_c/dbg_io.c b/arch/mips/momentum/ocelot_c/dbg_io.c
deleted file mode 100644
index 32d6fb4ee679..000000000000
--- a/arch/mips/momentum/ocelot_c/dbg_io.c
+++ /dev/null
@@ -1,121 +0,0 @@
1
2#include <asm/serial.h> /* For the serial port location and base baud */
3
4/* --- CONFIG --- */
5
6typedef unsigned char uint8;
7typedef unsigned int uint32;
8
9/* --- END OF CONFIG --- */
10
11#define UART16550_BAUD_2400 2400
12#define UART16550_BAUD_4800 4800
13#define UART16550_BAUD_9600 9600
14#define UART16550_BAUD_19200 19200
15#define UART16550_BAUD_38400 38400
16#define UART16550_BAUD_57600 57600
17#define UART16550_BAUD_115200 115200
18
19#define UART16550_PARITY_NONE 0
20#define UART16550_PARITY_ODD 0x08
21#define UART16550_PARITY_EVEN 0x18
22#define UART16550_PARITY_MARK 0x28
23#define UART16550_PARITY_SPACE 0x38
24
25#define UART16550_DATA_5BIT 0x0
26#define UART16550_DATA_6BIT 0x1
27#define UART16550_DATA_7BIT 0x2
28#define UART16550_DATA_8BIT 0x3
29
30#define UART16550_STOP_1BIT 0x0
31#define UART16550_STOP_2BIT 0x4
32
33/* ----------------------------------------------------- */
34
35/* === CONFIG === */
36
37/* [jsun] we use the second serial port for kdb */
38#define BASE OCELOT_SERIAL1_BASE
39#define MAX_BAUD OCELOT_BASE_BAUD
40
41/* === END OF CONFIG === */
42
43#define REG_OFFSET 4
44
45/* register offset */
46#define OFS_RCV_BUFFER 0
47#define OFS_TRANS_HOLD 0
48#define OFS_SEND_BUFFER 0
49#define OFS_INTR_ENABLE (1*REG_OFFSET)
50#define OFS_INTR_ID (2*REG_OFFSET)
51#define OFS_DATA_FORMAT (3*REG_OFFSET)
52#define OFS_LINE_CONTROL (3*REG_OFFSET)
53#define OFS_MODEM_CONTROL (4*REG_OFFSET)
54#define OFS_RS232_OUTPUT (4*REG_OFFSET)
55#define OFS_LINE_STATUS (5*REG_OFFSET)
56#define OFS_MODEM_STATUS (6*REG_OFFSET)
57#define OFS_RS232_INPUT (6*REG_OFFSET)
58#define OFS_SCRATCH_PAD (7*REG_OFFSET)
59
60#define OFS_DIVISOR_LSB (0*REG_OFFSET)
61#define OFS_DIVISOR_MSB (1*REG_OFFSET)
62
63
64/* memory-mapped read/write of the port */
65#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
66#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
67
68void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
69{
70 /* disable interrupts */
71 UART16550_WRITE(OFS_INTR_ENABLE, 0);
72
73 /* set up baud rate */
74 {
75 uint32 divisor;
76
77 /* set DIAB bit */
78 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
79
80 /* set divisor */
81 divisor = MAX_BAUD / baud;
82 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
83 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
84
85 /* clear DIAB bit */
86 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
87 }
88
89 /* set data format */
90 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
91}
92
93static int remoteDebugInitialized = 0;
94
95uint8 getDebugChar(void)
96{
97 if (!remoteDebugInitialized) {
98 remoteDebugInitialized = 1;
99 debugInit(UART16550_BAUD_38400,
100 UART16550_DATA_8BIT,
101 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
102 }
103
104 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
105 return UART16550_READ(OFS_RCV_BUFFER);
106}
107
108
109int putDebugChar(uint8 byte)
110{
111 if (!remoteDebugInitialized) {
112 remoteDebugInitialized = 1;
113 debugInit(UART16550_BAUD_38400,
114 UART16550_DATA_8BIT,
115 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
116 }
117
118 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
119 UART16550_WRITE(OFS_SEND_BUFFER, byte);
120 return 1;
121}
diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c
deleted file mode 100644
index 844d566c9de3..000000000000
--- a/arch/mips/momentum/ocelot_c/irq.c
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 *
30 */
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/kernel_stat.h>
34#include <linux/module.h>
35#include <linux/signal.h>
36#include <linux/sched.h>
37#include <linux/types.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/timex.h>
41#include <linux/slab.h>
42#include <linux/random.h>
43#include <linux/bitops.h>
44#include <linux/mv643xx.h>
45#include <asm/bootinfo.h>
46#include <asm/io.h>
47#include <asm/irq_cpu.h>
48#include <asm/mipsregs.h>
49#include <asm/system.h>
50
51extern void uart_irq_init(void);
52extern void cpci_irq_init(void);
53
54static struct irqaction cascade_fpga = {
55 no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via FPGA", NULL, NULL
56};
57
58static struct irqaction cascade_mv64340 = {
59 no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
60};
61
62extern void ll_uart_irq(void);
63extern void ll_cpci_irq(void);
64
65asmlinkage void plat_irq_dispatch(void)
66{
67 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
68
69 if (pending & STATUSF_IP0)
70 do_IRQ(0);
71 else if (pending & STATUSF_IP1)
72 do_IRQ(1);
73 else if (pending & STATUSF_IP2)
74 do_IRQ(2);
75 else if (pending & STATUSF_IP3)
76 ll_uart_irq();
77 else if (pending & STATUSF_IP4)
78 do_IRQ(4);
79 else if (pending & STATUSF_IP5)
80 ll_cpci_irq();
81 else if (pending & STATUSF_IP6)
82 ll_mv64340_irq();
83 else if (pending & STATUSF_IP7)
84 do_IRQ(7);
85 else
86 spurious_interrupt();
87}
88
89void __init arch_init_irq(void)
90{
91 /*
92 * Clear all of the interrupts while we change the able around a bit.
93 * int-handler is not on bootstrap
94 */
95 clear_c0_status(ST0_IM);
96
97 mips_cpu_irq_init();
98
99 /* set up the cascading interrupts */
100 setup_irq(3, &cascade_fpga);
101 setup_irq(5, &cascade_fpga);
102 setup_irq(6, &cascade_mv64340);
103
104 mv64340_irq_init(16);
105 uart_irq_init();
106 cpci_irq_init();
107}
diff --git a/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h b/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
deleted file mode 100644
index f0f5581dcb50..000000000000
--- a/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * Ocelot-C Board Register Definitions
3 *
4 * (C) 2002 Momentum Computer Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Louis Hamilton, Red Hat, Inc.
27 * hamilton@redhat.com [MIPS64 modifications]
28 */
29
30#ifndef __OCELOT_C_FPGA_H__
31#define __OCELOT_C_FPGA_H__
32
33
34#ifdef CONFIG_64BIT
35#define OCELOT_C_CS0_ADDR (0xfffffffffc000000)
36#else
37#define OCELOT_C_CS0_ADDR (0xfc000000)
38#endif
39
40#define OCELOT_C_REG_BOARDREV 0x0
41#define OCELOT_C_REG_FPGA_REV 0x1
42#define OCELOT_C_REG_FPGA_TYPE 0x2
43#define OCELOT_C_REG_RESET_STATUS 0x3
44#define OCELOT_C_REG_BOARD_STATUS 0x4
45#define OCELOT_C_REG_CPCI_ID 0x5
46#define OCELOT_C_REG_SET 0x6
47#define OCELOT_C_REG_CLR 0x7
48#define OCELOT_C_REG_EEPROM_MODE 0x9
49#define OCELOT_C_REG_INTMASK 0xa
50#define OCELOT_C_REG_INTSTAT 0xb
51#define OCELOT_C_REG_UART_INTMASK 0xc
52#define OCELOT_C_REG_UART_INTSTAT 0xd
53#define OCELOT_C_REG_INTSET 0xe
54#define OCELOT_C_REG_INTCLR 0xf
55
56#define __FPGA_REG_TO_ADDR(reg) \
57 ((void *) OCELOT_C_CS0_ADDR + OCELOT_C_REG_##reg)
58#define OCELOT_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
59#define OCELOT_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
60
61#endif
diff --git a/arch/mips/momentum/ocelot_c/platform.c b/arch/mips/momentum/ocelot_c/platform.c
deleted file mode 100644
index 7780aa0c6555..000000000000
--- a/arch/mips/momentum/ocelot_c/platform.c
+++ /dev/null
@@ -1,183 +0,0 @@
1#include <linux/delay.h>
2#include <linux/if_ether.h>
3#include <linux/ioport.h>
4#include <linux/mv643xx.h>
5#include <linux/platform_device.h>
6
7#include "ocelot_c_fpga.h"
8
9#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
10
11static struct resource mv643xx_eth_shared_resources[] = {
12 [0] = {
13 .name = "ethernet shared base",
14 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
15 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
16 MV643XX_ETH_SHARED_REGS_SIZE - 1,
17 .flags = IORESOURCE_MEM,
18 },
19};
20
21static struct platform_device mv643xx_eth_shared_device = {
22 .name = MV643XX_ETH_SHARED_NAME,
23 .id = 0,
24 .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
25 .resource = mv643xx_eth_shared_resources,
26};
27
28#define MV_SRAM_BASE 0xfe000000UL
29#define MV_SRAM_SIZE (256 * 1024)
30
31#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
32#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
33
34#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
35#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
36
37#define MV64x60_IRQ_ETH_0 48
38#define MV64x60_IRQ_ETH_1 49
39
40static struct resource mv64x60_eth0_resources[] = {
41 [0] = {
42 .name = "eth0 irq",
43 .start = MV64x60_IRQ_ETH_0,
44 .end = MV64x60_IRQ_ETH_0,
45 .flags = IORESOURCE_IRQ,
46 },
47};
48
49static struct mv643xx_eth_platform_data eth0_pd = {
50 .port_number = 0,
51
52 .tx_sram_addr = MV_SRAM_BASE_ETH0,
53 .tx_sram_size = MV_SRAM_TXRING_SIZE,
54 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
55
56 .rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
57 .rx_sram_size = MV_SRAM_RXRING_SIZE,
58 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
59};
60
61static struct platform_device eth0_device = {
62 .name = MV643XX_ETH_NAME,
63 .id = 0,
64 .num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
65 .resource = mv64x60_eth0_resources,
66 .dev = {
67 .platform_data = &eth0_pd,
68 },
69};
70
71static struct resource mv64x60_eth1_resources[] = {
72 [0] = {
73 .name = "eth1 irq",
74 .start = MV64x60_IRQ_ETH_1,
75 .end = MV64x60_IRQ_ETH_1,
76 .flags = IORESOURCE_IRQ,
77 },
78};
79
80static struct mv643xx_eth_platform_data eth1_pd = {
81 .port_number = 1,
82
83 .tx_sram_addr = MV_SRAM_BASE_ETH1,
84 .tx_sram_size = MV_SRAM_TXRING_SIZE,
85 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
86
87 .rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
88 .rx_sram_size = MV_SRAM_RXRING_SIZE,
89 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
90};
91
92static struct platform_device eth1_device = {
93 .name = MV643XX_ETH_NAME,
94 .id = 1,
95 .num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
96 .resource = mv64x60_eth1_resources,
97 .dev = {
98 .platform_data = &eth1_pd,
99 },
100};
101
102static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
103 &mv643xx_eth_shared_device,
104 &eth0_device,
105 &eth1_device,
106 /* The third port is not wired up on the Ocelot C */
107};
108
109static u8 __init exchange_bit(u8 val, u8 cs)
110{
111 /* place the data */
112 OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
113 udelay(1);
114
115 /* turn the clock on */
116 OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
117 udelay(1);
118
119 /* turn the clock off and read-strobe */
120 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
121
122 /* return the data */
123 return (OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
124}
125
126static void __init get_mac(char dest[6])
127{
128 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
129 int i,j;
130
131 for (i = 0; i < 12; i++)
132 exchange_bit(read_opcode[i], 1);
133
134 for (j = 0; j < 6; j++) {
135 dest[j] = 0;
136 for (i = 0; i < 8; i++) {
137 dest[j] <<= 1;
138 dest[j] |= exchange_bit(0, 1);
139 }
140 }
141
142 /* turn off CS */
143 exchange_bit(0,0);
144}
145
146/*
147 * Copy and increment ethernet MAC address by a small value.
148 *
149 * This is useful for systems where the only one MAC address is stored in
150 * non-volatile memory for multiple ports.
151 */
152static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
153 unsigned int add)
154{
155 int i;
156
157 BUG_ON(add >= 256);
158
159 for (i = ETH_ALEN; i >= 0; i--) {
160 dst[i] = src[i] + add;
161 add = dst[i] < src[i]; /* compute carry */
162 }
163
164 WARN_ON(add);
165}
166
167static int __init mv643xx_eth_add_pds(void)
168{
169 unsigned char mac[ETH_ALEN];
170 int ret;
171
172 get_mac(mac);
173 eth_mac_add(eth0_pd.mac_addr, mac, 0);
174 eth_mac_add(eth1_pd.mac_addr, mac, 1);
175 ret = platform_add_devices(mv643xx_eth_pd_devs,
176 ARRAY_SIZE(mv643xx_eth_pd_devs));
177
178 return ret;
179}
180
181device_initcall(mv643xx_eth_add_pds);
182
183#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
diff --git a/arch/mips/momentum/ocelot_c/prom.c b/arch/mips/momentum/ocelot_c/prom.c
deleted file mode 100644
index b689ceea8cfb..000000000000
--- a/arch/mips/momentum/ocelot_c/prom.c
+++ /dev/null
@@ -1,183 +0,0 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Louis Hamilton, Red Hat, Inc.
6 * hamilton@redhat.com [MIPS64 modifications]
7 *
8 * Based on Ocelot Linux port, which is
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: jsun@mvista.com or jsun@junsun.net
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#include <linux/init.h>
18#include <linux/mm.h>
19#include <linux/sched.h>
20#include <linux/bootmem.h>
21#include <linux/mv643xx.h>
22
23#include <asm/addrspace.h>
24#include <asm/bootinfo.h>
25#include <asm/pmon.h>
26
27#include "ocelot_c_fpga.h"
28
29struct callvectors* debug_vectors;
30
31extern unsigned long marvell_base;
32extern unsigned int cpu_clock;
33
34const char *get_system_type(void)
35{
36#ifdef CONFIG_CPU_SR71000
37 return "Momentum Ocelot-CS";
38#else
39 return "Momentum Ocelot-C";
40#endif
41}
42
43#ifdef CONFIG_64BIT
44
45unsigned long signext(unsigned long addr)
46{
47 addr &= 0xffffffff;
48 return (unsigned long)((int)addr);
49}
50
51void *get_arg(unsigned long args, int arc)
52{
53 unsigned long ul;
54 unsigned char *puc, uc;
55
56 args += (arc * 4);
57 ul = (unsigned long)signext(args);
58 puc = (unsigned char *)ul;
59 if (puc == 0)
60 return (void *)0;
61
62#ifdef CONFIG_CPU_LITTLE_ENDIAN
63 uc = *puc++;
64 ul = (unsigned long)uc;
65 uc = *puc++;
66 ul |= (((unsigned long)uc) << 8);
67 uc = *puc++;
68 ul |= (((unsigned long)uc) << 16);
69 uc = *puc++;
70 ul |= (((unsigned long)uc) << 24);
71#else /* CONFIG_CPU_LITTLE_ENDIAN */
72 uc = *puc++;
73 ul = ((unsigned long)uc) << 24;
74 uc = *puc++;
75 ul |= (((unsigned long)uc) << 16);
76 uc = *puc++;
77 ul |= (((unsigned long)uc) << 8);
78 uc = *puc++;
79 ul |= ((unsigned long)uc);
80#endif /* CONFIG_CPU_LITTLE_ENDIAN */
81 ul = signext(ul);
82 return (void *)ul;
83}
84
85char *arg64(unsigned long addrin, int arg_index)
86{
87 unsigned long args;
88 char *p;
89 args = signext(addrin);
90 p = (char *)get_arg(args, arg_index);
91 return p;
92}
93#endif /* CONFIG_64BIT */
94
95
96void __init prom_init(void)
97{
98 int argc = fw_arg0;
99 char **arg = (char **) fw_arg1;
100 char **env = (char **) fw_arg2;
101 struct callvectors *cv = (struct callvectors *) fw_arg3;
102 int i;
103
104#ifdef CONFIG_64BIT
105 char *ptr;
106
107 printk("prom_init - MIPS64\n");
108 /* save the PROM vectors for debugging use */
109 debug_vectors = (struct callvectors *)signext((unsigned long)cv);
110
111 /* arg[0] is "g", the rest is boot parameters */
112 arcs_cmdline[0] = '\0';
113
114 for (i = 1; i < argc; i++) {
115 ptr = (char *)arg64((unsigned long)arg, i);
116 if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
117 sizeof(arcs_cmdline))
118 break;
119 strcat(arcs_cmdline, ptr);
120 strcat(arcs_cmdline, " ");
121 }
122 i = 0;
123 while (1) {
124 ptr = (char *)arg64((unsigned long)env, i);
125 if (! ptr)
126 break;
127
128 if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
129 marvell_base = simple_strtol(ptr + strlen("gtbase="),
130 NULL, 16);
131
132 if ((marvell_base & 0xffffffff00000000) == 0)
133 marvell_base |= 0xffffffff00000000;
134
135 printk("marvell_base set to 0x%016lx\n", marvell_base);
136 }
137 if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
138 cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
139 NULL, 10);
140 printk("cpu_clock set to %d\n", cpu_clock);
141 }
142 i++;
143 }
144 printk("arcs_cmdline: %s\n", arcs_cmdline);
145
146#else /* CONFIG_64BIT */
147 /* save the PROM vectors for debugging use */
148 debug_vectors = cv;
149
150 /* arg[0] is "g", the rest is boot parameters */
151 arcs_cmdline[0] = '\0';
152 for (i = 1; i < argc; i++) {
153 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
154 >= sizeof(arcs_cmdline))
155 break;
156 strcat(arcs_cmdline, arg[i]);
157 strcat(arcs_cmdline, " ");
158 }
159
160 while (*env) {
161 if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
162 marvell_base = simple_strtol(*env + strlen("gtbase="),
163 NULL, 16);
164 }
165 if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
166 cpu_clock = simple_strtol(*env + strlen("cpuclock="),
167 NULL, 10);
168 }
169 env++;
170 }
171#endif /* CONFIG_64BIT */
172
173 mips_machgroup = MACH_GROUP_MOMENCO;
174 mips_machtype = MACH_MOMENCO_OCELOT_C;
175
176#ifndef CONFIG_64BIT
177 debug_vectors->printf("Booting Linux kernel...\n");
178#endif
179}
180
181void __init prom_free_prom_memory(void)
182{
183}
diff --git a/arch/mips/momentum/ocelot_c/reset.c b/arch/mips/momentum/ocelot_c/reset.c
deleted file mode 100644
index 3fdcb64ff1e6..000000000000
--- a/arch/mips/momentum/ocelot_c/reset.c
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 * Copyright (C) 2002 Momentum Computer Inc.
12 * Author: Matthew Dharm <mdharm@momenco.com>
13 *
14 * Louis Hamilton, Red Hat, Inc.
15 * hamilton@redhat.com [MIPS64 modifications]
16 */
17#include <linux/sched.h>
18#include <linux/mm.h>
19#include <asm/io.h>
20#include <asm/pgtable.h>
21#include <asm/processor.h>
22#include <asm/reboot.h>
23#include <asm/system.h>
24#include <linux/delay.h>
25
26void momenco_ocelot_restart(char *command)
27{
28 /* base address of timekeeper portion of part */
29 void *nvram = (void *)
30#ifdef CONFIG_64BIT
31 0xfffffffffc807000;
32#else
33 0xfc807000;
34#endif
35
36 /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
37 writeb(0x84, nvram + 0xff7);
38
39 /* wait for the watchdog to go off */
40 mdelay(100+(1000/16));
41
42 /* if the watchdog fails for some reason, let people know */
43 printk(KERN_NOTICE "Watchdog reset failed\n");
44}
45
46void momenco_ocelot_halt(void)
47{
48 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
49 while (1)
50 __asm__(".set\tmips3\n\t"
51 "wait\n\t"
52 ".set\tmips0");
53}
54
55void momenco_ocelot_power_off(void)
56{
57 momenco_ocelot_halt();
58}
diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c
deleted file mode 100644
index 0b6b2338cfb4..000000000000
--- a/arch/mips/momentum/ocelot_c/setup.c
+++ /dev/null
@@ -1,362 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Ocelot-C and -CS board dependent boot routines
4 *
5 * Copyright (C) 1996, 1997, 2001 Ralf Baechle
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
9 *
10 * Author: Matthew Dharm, Momentum Computer
11 * mdharm@momenco.com
12 *
13 * Louis Hamilton, Red Hat, Inc.
14 * hamilton@redhat.com [MIPS64 modifications]
15 *
16 * Author: RidgeRun, Inc.
17 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
18 *
19 * Copyright 2001 MontaVista Software Inc.
20 * Author: jsun@mvista.com or jsun@junsun.net
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License as published by the
24 * Free Software Foundation; either version 2 of the License, or (at your
25 * option) any later version.
26 *
27 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
30 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
33 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * You should have received a copy of the GNU General Public License along
39 * with this program; if not, write to the Free Software Foundation, Inc.,
40 * 675 Mass Ave, Cambridge, MA 02139, USA.
41 *
42 */
43#include <linux/bcd.h>
44#include <linux/init.h>
45#include <linux/kernel.h>
46#include <linux/types.h>
47#include <linux/mm.h>
48#include <linux/swap.h>
49#include <linux/ioport.h>
50#include <linux/sched.h>
51#include <linux/interrupt.h>
52#include <linux/pci.h>
53#include <linux/pm.h>
54#include <linux/timex.h>
55#include <linux/vmalloc.h>
56#include <linux/mv643xx.h>
57
58#include <asm/time.h>
59#include <asm/bootinfo.h>
60#include <asm/page.h>
61#include <asm/io.h>
62#include <asm/irq.h>
63#include <asm/pci.h>
64#include <asm/processor.h>
65#include <asm/reboot.h>
66#include <asm/marvell.h>
67#include <linux/bootmem.h>
68#include <linux/blkdev.h>
69#include "ocelot_c_fpga.h"
70
71unsigned long marvell_base;
72unsigned int cpu_clock;
73
74/* These functions are used for rebooting or halting the machine*/
75extern void momenco_ocelot_restart(char *command);
76extern void momenco_ocelot_halt(void);
77extern void momenco_ocelot_power_off(void);
78
79void momenco_time_init(void);
80
81static char reset_reason;
82
83void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask);
84
85static unsigned long ENTRYLO(unsigned long paddr)
86{
87 return ((paddr & PAGE_MASK) |
88 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
89 _CACHE_UNCACHED)) >> 6;
90}
91
92/* setup code for a handoff from a version 2 PMON 2000 PROM */
93void PMON_v2_setup(void)
94{
95 /* Some wired TLB entries for the MV64340 and perhiperals. The
96 MV64340 is going to be hit on every IRQ anyway - there's
97 absolutely no point in letting it be a random TLB entry, as
98 it'll just cause needless churning of the TLB. And we use
99 the other half for the serial port, which is just a PITA
100 otherwise :)
101
102 Device Physical Virtual
103 MV64340 Internal Regs 0xf4000000 0xf4000000
104 Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
105 NVRAM (CS1) 0xfc800000 0xfc800000
106 UARTs (CS2) 0xfd000000 0xfd000000
107 Internal SRAM 0xfe000000 0xfe000000
108 M-Systems DOC (CS3) 0xff000000 0xff000000
109 */
110 printk("PMON_v2_setup\n");
111
112#ifdef CONFIG_64BIT
113 /* marvell and extra space */
114 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K);
115 /* fpga, rtc, and uart */
116 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfffffffffc000000, PM_16M);
117 /* m-sys and internal SRAM */
118 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
119
120 marvell_base = 0xfffffffff4000000;
121#else
122 /* marvell and extra space */
123 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
124 /* fpga, rtc, and uart */
125 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M);
126 /* m-sys and internal SRAM */
127 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
128
129 marvell_base = 0xf4000000;
130#endif
131}
132
133unsigned long m48t37y_get_time(void)
134{
135#ifdef CONFIG_64BIT
136 unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000;
137#else
138 unsigned char* rtc_base = (unsigned char*)0xfc800000;
139#endif
140 unsigned int year, month, day, hour, min, sec;
141 unsigned long flags;
142
143 spin_lock_irqsave(&rtc_lock, flags);
144 /* stop the update */
145 rtc_base[0x7ff8] = 0x40;
146
147 year = BCD2BIN(rtc_base[0x7fff]);
148 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
149
150 month = BCD2BIN(rtc_base[0x7ffe]);
151
152 day = BCD2BIN(rtc_base[0x7ffd]);
153
154 hour = BCD2BIN(rtc_base[0x7ffb]);
155 min = BCD2BIN(rtc_base[0x7ffa]);
156 sec = BCD2BIN(rtc_base[0x7ff9]);
157
158 /* start the update */
159 rtc_base[0x7ff8] = 0x00;
160 spin_unlock_irqrestore(&rtc_lock, flags);
161
162 return mktime(year, month, day, hour, min, sec);
163}
164
165int m48t37y_set_time(unsigned long sec)
166{
167#ifdef CONFIG_64BIT
168 unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000;
169#else
170 unsigned char* rtc_base = (unsigned char*)0xfc800000;
171#endif
172 struct rtc_time tm;
173 unsigned long flags;
174
175 /* convert to a more useful format -- note months count from 0 */
176 to_tm(sec, &tm);
177 tm.tm_mon += 1;
178
179 spin_lock_irqsave(&rtc_lock, flags);
180 /* enable writing */
181 rtc_base[0x7ff8] = 0x80;
182
183 /* year */
184 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
185 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
186
187 /* month */
188 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
189
190 /* day */
191 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
192
193 /* hour/min/sec */
194 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
195 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
196 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
197
198 /* day of week -- not really used, but let's keep it up-to-date */
199 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
200
201 /* disable writing */
202 rtc_base[0x7ff8] = 0x00;
203 spin_unlock_irqrestore(&rtc_lock, flags);
204
205 return 0;
206}
207
208void __init plat_timer_setup(struct irqaction *irq)
209{
210 setup_irq(7, irq);
211}
212
213void momenco_time_init(void)
214{
215#ifdef CONFIG_CPU_SR71000
216 mips_hpt_frequency = cpu_clock;
217#elif defined(CONFIG_CPU_RM7000)
218 mips_hpt_frequency = cpu_clock / 2;
219#else
220#error Unknown CPU for this board
221#endif
222 printk("momenco_time_init cpu_clock=%d\n", cpu_clock);
223
224 rtc_mips_get_time = m48t37y_get_time;
225 rtc_mips_set_time = m48t37y_set_time;
226}
227
228void __init plat_mem_setup(void)
229{
230 unsigned int tmpword;
231
232 board_time_init = momenco_time_init;
233
234 _machine_restart = momenco_ocelot_restart;
235 _machine_halt = momenco_ocelot_halt;
236 pm_power_off = momenco_ocelot_power_off;
237
238 /*
239 * initrd_start = (unsigned long)ocelot_initrd_start;
240 * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
241 * initrd_below_start_ok = 1;
242 */
243
244 /* do handoff reconfiguration */
245 PMON_v2_setup();
246
247 /* shut down ethernet ports, just to be sure our memory doesn't get
248 * corrupted by random ethernet traffic.
249 */
250 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
251 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
252 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
253 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
254 do {}
255 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
256 do {}
257 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
258 do {}
259 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
260 do {}
261 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
262 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
263 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
264 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
265 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
266
267 /* Turn off the Bit-Error LED */
268 OCELOT_FPGA_WRITE(0x80, CLR);
269
270 tmpword = OCELOT_FPGA_READ(BOARDREV);
271#ifdef CONFIG_CPU_SR71000
272 if (tmpword < 26)
273 printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n",
274 'A'+tmpword);
275 else
276 printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n",
277 tmpword);
278#else
279 if (tmpword < 26)
280 printk("Momenco Ocelot-C: Board Assembly Rev. %c\n",
281 'A'+tmpword);
282 else
283 printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n",
284 tmpword);
285#endif
286
287 tmpword = OCELOT_FPGA_READ(FPGA_REV);
288 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
289 tmpword = OCELOT_FPGA_READ(RESET_STATUS);
290 printk("Reset reason: 0x%x\n", tmpword);
291 switch (tmpword) {
292 case 0x1:
293 printk(" - Power-up reset\n");
294 break;
295 case 0x2:
296 printk(" - Push-button reset\n");
297 break;
298 case 0x4:
299 printk(" - cPCI bus reset\n");
300 break;
301 case 0x8:
302 printk(" - Watchdog reset\n");
303 break;
304 case 0x10:
305 printk(" - Software reset\n");
306 break;
307 default:
308 printk(" - Unknown reset cause\n");
309 }
310 reset_reason = tmpword;
311 OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
312
313 tmpword = OCELOT_FPGA_READ(CPCI_ID);
314 printk("cPCI ID register: 0x%02x\n", tmpword);
315 printk(" - Slot number: %d\n", tmpword & 0x1f);
316 printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
317 printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
318
319 tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
320 printk("Board Status register: 0x%02x\n", tmpword);
321 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
322 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
323 printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
324 printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
325
326 switch(tmpword &3) {
327 case 3:
328 /* 512MiB */
329 add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM);
330 break;
331 case 2:
332 /* 256MiB */
333 add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
334 break;
335 case 1:
336 /* 128MiB */
337 add_memory_region(0x0, 0x80<<20, BOOT_MEM_RAM);
338 break;
339 case 0:
340 /* 1GiB -- needs CONFIG_HIGHMEM */
341 add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM);
342 break;
343 }
344}
345
346/*
347 * This needs to be one of the first initcalls, because no I/O port access
348 * can work before this
349 */
350static int io_base_ioremap(void)
351{
352 void __iomem * io_remap_range = ioremap(0xc0000000UL, 0x10000);
353
354 if (!io_remap_range)
355 panic("Could not ioremap I/O port range");
356
357 set_io_port_base((unsigned long) io_remap_range);
358
359 return 0;
360}
361
362module_init(io_base_ioremap);
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
deleted file mode 100644
index de1a31ee52f3..000000000000
--- a/arch/mips/momentum/ocelot_c/uart-irq.c
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * Copyright 2002 Momentum Computer
3 * Author: mdharm@momenco.com
4 *
5 * arch/mips/momentum/ocelot_c/uart-irq.c
6 * Interrupt routines for UARTs. Interrupt numbers are assigned from
7 * 80 to 81 (2 interrupt sources).
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/kernel_stat.h>
21#include <asm/io.h>
22#include <asm/irq.h>
23#include "ocelot_c_fpga.h"
24
25static inline int ls1bit8(unsigned int x)
26{
27 int b = 7, s;
28
29 s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
30 s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
31 s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
32
33 return b;
34}
35
36/* mask off an interrupt -- 0 is enable, 1 is disable */
37static inline void mask_uart_irq(unsigned int irq)
38{
39 uint8_t value;
40
41 value = OCELOT_FPGA_READ(UART_INTMASK);
42 value |= 1 << (irq - 74);
43 OCELOT_FPGA_WRITE(value, UART_INTMASK);
44
45 /* read the value back to assure that it's really been written */
46 value = OCELOT_FPGA_READ(UART_INTMASK);
47}
48
49/* unmask an interrupt -- 0 is enable, 1 is disable */
50static inline void unmask_uart_irq(unsigned int irq)
51{
52 uint8_t value;
53
54 value = OCELOT_FPGA_READ(UART_INTMASK);
55 value &= ~(1 << (irq - 74));
56 OCELOT_FPGA_WRITE(value, UART_INTMASK);
57
58 /* read the value back to assure that it's really been written */
59 value = OCELOT_FPGA_READ(UART_INTMASK);
60}
61
62/*
63 * Interrupt handler for interrupts coming from the FPGA chip.
64 */
65void ll_uart_irq(void)
66{
67 unsigned int irq_src, irq_mask;
68
69 /* read the interrupt status registers */
70 irq_src = OCELOT_FPGA_READ(UART_INTSTAT);
71 irq_mask = OCELOT_FPGA_READ(UART_INTMASK);
72
73 /* mask for just the interrupts we want */
74 irq_src &= ~irq_mask;
75
76 do_IRQ(ls1bit8(irq_src) + 74);
77}
78
79struct irq_chip uart_irq_type = {
80 .name = "UART/FPGA",
81 .ack = mask_uart_irq,
82 .mask = mask_uart_irq,
83 .mask_ack = mask_uart_irq,
84 .unmask = unmask_uart_irq,
85};
86
87void uart_irq_init(void)
88{
89 set_irq_chip_and_handler(80, &uart_irq_type, handle_level_irq);
90 set_irq_chip_and_handler(81, &uart_irq_type, handle_level_irq);
91}
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