aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/momentum/ocelot_c
diff options
context:
space:
mode:
authorRalf Baechle <ralf@linux-mips.org>2006-04-03 12:56:36 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-04-18 22:14:21 -0400
commite4ac58afdfac792c0583af30dbd9eae53e24c78b (patch)
tree7517bef2c515fc630e4d3d238867b91cde96f558 /arch/mips/momentum/ocelot_c
parentd35d473c25d43d7db3e5e18b66d558d2a631cca8 (diff)
[MIPS] Rewrite all the assembler interrupt handlers to C.
Saves like 1,600 lines of code, is way easier to debug, compilers frequently do a better job than the cut and paste type of handlers many boards had. And finally having all the stuff done in a single place also means alot of bug potencial for the MT ASE is gone. The only surviving handler in assembler is the DECstation one; I hope Maciej will rewrite it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/momentum/ocelot_c')
-rw-r--r--arch/mips/momentum/ocelot_c/Makefile2
-rw-r--r--arch/mips/momentum/ocelot_c/int-handler.S103
-rw-r--r--arch/mips/momentum/ocelot_c/irq.c30
3 files changed, 28 insertions, 107 deletions
diff --git a/arch/mips/momentum/ocelot_c/Makefile b/arch/mips/momentum/ocelot_c/Makefile
index 91240777f978..94802b4db472 100644
--- a/arch/mips/momentum/ocelot_c/Makefile
+++ b/arch/mips/momentum/ocelot_c/Makefile
@@ -2,7 +2,7 @@
2# Makefile for Momentum Computer's Ocelot-C and -CS boards. 2# Makefile for Momentum Computer's Ocelot-C and -CS boards.
3# 3#
4 4
5obj-y += cpci-irq.o int-handler.o irq.o prom.o reset.o \ 5obj-y += cpci-irq.o irq.o prom.o reset.o \
6 setup.o uart-irq.o 6 setup.o uart-irq.o
7 7
8obj-$(CONFIG_KGDB) += dbg_io.o 8obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/momentum/ocelot_c/int-handler.S b/arch/mips/momentum/ocelot_c/int-handler.S
deleted file mode 100644
index f77834193c3c..000000000000
--- a/arch/mips/momentum/ocelot_c/int-handler.S
+++ /dev/null
@@ -1,103 +0,0 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: jsun@mvista.com or jsun@junsun.net
7 *
8 * First-level interrupt dispatcher for Ocelot-CS board.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#include <asm/asm.h>
16#include <asm/mipsregs.h>
17#include <asm/addrspace.h>
18#include <asm/regdef.h>
19#include <asm/stackframe.h>
20#include "ocelot_c_fpga.h"
21
22/*
23 * First level interrupt dispatcher for Ocelot-CS board
24 */
25 .align 5
26 NESTED(ocelot_handle_int, PT_SIZE, sp)
27 SAVE_ALL
28 CLI
29 .set at
30 mfc0 t0, CP0_CAUSE
31 mfc0 t2, CP0_STATUS
32
33 and t0, t2
34
35 andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */
36 bnez t1, ll_sw0_irq
37 andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */
38 bnez t1, ll_sw1_irq
39 andi t1, t0, STATUSF_IP2 /* int0 hardware line */
40 bnez t1, ll_scsi_irq
41 andi t1, t0, STATUSF_IP3 /* int1 hardware line */
42 bnez t1, ll_uart_decode_irq
43 andi t1, t0, STATUSF_IP4 /* int2 hardware line */
44 bnez t1, ll_pmc_irq
45 andi t1, t0, STATUSF_IP5 /* int3 hardware line */
46 bnez t1, ll_cpci_decode_irq
47 andi t1, t0, STATUSF_IP6 /* int4 hardware line */
48 bnez t1, ll_mv64340_decode_irq
49 andi t1, t0, STATUSF_IP7 /* cpu timer */
50 bnez t1, ll_cputimer_irq
51
52 .set reorder
53
54 /* wrong alarm or masked ... */
55 jal spurious_interrupt
56 nop
57 j ret_from_irq
58 END(ocelot_handle_int)
59
60 .align 5
61ll_sw0_irq:
62 li a0, 0
63 move a1, sp
64 jal do_IRQ
65 j ret_from_irq
66ll_sw1_irq:
67 li a0, 1
68 move a1, sp
69 jal do_IRQ
70 j ret_from_irq
71ll_scsi_irq:
72 li a0, 2
73 move a1, sp
74 jal do_IRQ
75 j ret_from_irq
76
77ll_uart_decode_irq:
78 move a0, sp
79 jal ll_uart_irq
80 j ret_from_irq
81
82ll_pmc_irq:
83 li a0, 4
84 move a1, sp
85 jal do_IRQ
86 j ret_from_irq
87
88ll_cpci_decode_irq:
89 move a0, sp
90 jal ll_cpci_irq
91 j ret_from_irq
92
93ll_mv64340_decode_irq:
94 move a0, sp
95 jal ll_mv64340_irq
96 j ret_from_irq
97
98ll_cputimer_irq:
99 li a0, 7
100 move a1, sp
101 jal do_IRQ
102 j ret_from_irq
103
diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c
index a5764bc20e36..86f61ce59e53 100644
--- a/arch/mips/momentum/ocelot_c/irq.c
+++ b/arch/mips/momentum/ocelot_c/irq.c
@@ -48,7 +48,6 @@
48#include <asm/mipsregs.h> 48#include <asm/mipsregs.h>
49#include <asm/system.h> 49#include <asm/system.h>
50 50
51extern asmlinkage void ocelot_handle_int(void);
52extern void uart_irq_init(void); 51extern void uart_irq_init(void);
53extern void cpci_irq_init(void); 52extern void cpci_irq_init(void);
54 53
@@ -60,6 +59,33 @@ static struct irqaction cascade_mv64340 = {
60 no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL 59 no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
61}; 60};
62 61
62extern void ll_uart_irq(struct pt_regs *regs);
63extern void ll_cpci_irq(struct pt_regs *regs);
64
65asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
66{
67 unsigned int pending = read_c0_cause() & read_c0_status();
68
69 if (pending & STATUSF_IP0)
70 do_IRQ(0, regs);
71 else if (pending & STATUSF_IP1)
72 do_IRQ(1, regs);
73 else if (pending & STATUSF_IP2)
74 do_IRQ(2, regs);
75 else if (pending & STATUSF_IP3)
76 ll_uart_irq(regs);
77 else if (pending & STATUSF_IP4)
78 do_IRQ(4, regs);
79 else if (pending & STATUSF_IP5)
80 ll_cpci_irq(regs);
81 else if (pending & STATUSF_IP6)
82 ll_mv64340_irq(regs);
83 else if (pending & STATUSF_IP7)
84 do_IRQ(7, regs);
85 else
86 spurious_interrupt(regs);
87}
88
63void __init arch_init_irq(void) 89void __init arch_init_irq(void)
64{ 90{
65 /* 91 /*
@@ -68,8 +94,6 @@ void __init arch_init_irq(void)
68 */ 94 */
69 clear_c0_status(ST0_IM); 95 clear_c0_status(ST0_IM);
70 96
71 /* Sets the first-level interrupt dispatcher. */
72 set_except_vector(0, ocelot_handle_int);
73 mips_cpu_irq_init(0); 97 mips_cpu_irq_init(0);
74 98
75 /* set up the cascading interrupts */ 99 /* set up the cascading interrupts */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-11 21:57:10 -0500