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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/momentum/ocelot_c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/mips/momentum/ocelot_c')
-rw-r--r--arch/mips/momentum/ocelot_c/Makefile8
-rw-r--r--arch/mips/momentum/ocelot_c/cpci-irq.c153
-rw-r--r--arch/mips/momentum/ocelot_c/dbg_io.c126
-rw-r--r--arch/mips/momentum/ocelot_c/int-handler.S102
-rw-r--r--arch/mips/momentum/ocelot_c/irq.c83
-rw-r--r--arch/mips/momentum/ocelot_c/ocelot_c_fpga.h60
-rw-r--r--arch/mips/momentum/ocelot_c/prom.c243
-rw-r--r--arch/mips/momentum/ocelot_c/reset.c59
-rw-r--r--arch/mips/momentum/ocelot_c/setup.c363
-rw-r--r--arch/mips/momentum/ocelot_c/uart-irq.c147
10 files changed, 1344 insertions, 0 deletions
diff --git a/arch/mips/momentum/ocelot_c/Makefile b/arch/mips/momentum/ocelot_c/Makefile
new file mode 100644
index 000000000000..91240777f978
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for Momentum Computer's Ocelot-C and -CS boards.
3#
4
5obj-y += cpci-irq.o int-handler.o irq.o prom.o reset.o \
6 setup.o uart-irq.o
7
8obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
new file mode 100644
index 000000000000..dea48b3ad687
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/cpci-irq.c
@@ -0,0 +1,153 @@
1/*
2 * Copyright 2002 Momentum Computer
3 * Author: mdharm@momenco.com
4 *
5 * arch/mips/momentum/ocelot_c/cpci-irq.c
6 * Interrupt routines for cpci. Interrupt numbers are assigned from
7 * CPCI_IRQ_BASE to CPCI_IRQ_BASE+8 (8 interrupt sources).
8 *
9 * Note that the high-level software will need to be careful about using
10 * these interrupts. If this board is asserting a cPCI interrupt, it will
11 * also see the asserted interrupt. Care must be taken to avoid an
12 * interrupt flood.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19
20#include <linux/module.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/kernel.h>
24#include <asm/ptrace.h>
25#include <linux/sched.h>
26#include <linux/kernel_stat.h>
27#include <asm/io.h>
28#include "ocelot_c_fpga.h"
29
30#define CPCI_IRQ_BASE 8
31
32static inline int ls1bit8(unsigned int x)
33{
34 int b = 7, s;
35
36 s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
37 s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
38 s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
39
40 return b;
41}
42
43/* mask off an interrupt -- 0 is enable, 1 is disable */
44static inline void mask_cpci_irq(unsigned int irq)
45{
46 uint32_t value;
47
48 value = OCELOT_FPGA_READ(INTMASK);
49 value |= 1 << (irq - CPCI_IRQ_BASE);
50 OCELOT_FPGA_WRITE(value, INTMASK);
51
52 /* read the value back to assure that it's really been written */
53 value = OCELOT_FPGA_READ(INTMASK);
54}
55
56/* unmask an interrupt -- 0 is enable, 1 is disable */
57static inline void unmask_cpci_irq(unsigned int irq)
58{
59 uint32_t value;
60
61 value = OCELOT_FPGA_READ(INTMASK);
62 value &= ~(1 << (irq - CPCI_IRQ_BASE));
63 OCELOT_FPGA_WRITE(value, INTMASK);
64
65 /* read the value back to assure that it's really been written */
66 value = OCELOT_FPGA_READ(INTMASK);
67}
68
69/*
70 * Enables the IRQ in the FPGA
71 */
72static void enable_cpci_irq(unsigned int irq)
73{
74 unmask_cpci_irq(irq);
75}
76
77/*
78 * Initialize the IRQ in the FPGA
79 */
80static unsigned int startup_cpci_irq(unsigned int irq)
81{
82 unmask_cpci_irq(irq);
83 return 0;
84}
85
86/*
87 * Disables the IRQ in the FPGA
88 */
89static void disable_cpci_irq(unsigned int irq)
90{
91 mask_cpci_irq(irq);
92}
93
94/*
95 * Masks and ACKs an IRQ
96 */
97static void mask_and_ack_cpci_irq(unsigned int irq)
98{
99 mask_cpci_irq(irq);
100}
101
102/*
103 * End IRQ processing
104 */
105static void end_cpci_irq(unsigned int irq)
106{
107 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
108 unmask_cpci_irq(irq);
109}
110
111/*
112 * Interrupt handler for interrupts coming from the FPGA chip.
113 * It could be built in ethernet ports etc...
114 */
115void ll_cpci_irq(struct pt_regs *regs)
116{
117 unsigned int irq_src, irq_mask;
118
119 /* read the interrupt status registers */
120 irq_src = OCELOT_FPGA_READ(INTSTAT);
121 irq_mask = OCELOT_FPGA_READ(INTMASK);
122
123 /* mask for just the interrupts we want */
124 irq_src &= ~irq_mask;
125
126 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE, regs);
127}
128
129#define shutdown_cpci_irq disable_cpci_irq
130
131struct hw_interrupt_type cpci_irq_type = {
132 "CPCI/FPGA",
133 startup_cpci_irq,
134 shutdown_cpci_irq,
135 enable_cpci_irq,
136 disable_cpci_irq,
137 mask_and_ack_cpci_irq,
138 end_cpci_irq,
139 NULL
140};
141
142void cpci_irq_init(void)
143{
144 int i;
145
146 /* Reset irq handlers pointers to NULL */
147 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) {
148 irq_desc[i].status = IRQ_DISABLED;
149 irq_desc[i].action = 0;
150 irq_desc[i].depth = 2;
151 irq_desc[i].handler = &cpci_irq_type;
152 }
153}
diff --git a/arch/mips/momentum/ocelot_c/dbg_io.c b/arch/mips/momentum/ocelot_c/dbg_io.c
new file mode 100644
index 000000000000..8720bccfdea2
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/dbg_io.c
@@ -0,0 +1,126 @@
1#include <linux/config.h>
2
3#ifdef CONFIG_KGDB
4
5#include <asm/serial.h> /* For the serial port location and base baud */
6
7/* --- CONFIG --- */
8
9typedef unsigned char uint8;
10typedef unsigned int uint32;
11
12/* --- END OF CONFIG --- */
13
14#define UART16550_BAUD_2400 2400
15#define UART16550_BAUD_4800 4800
16#define UART16550_BAUD_9600 9600
17#define UART16550_BAUD_19200 19200
18#define UART16550_BAUD_38400 38400
19#define UART16550_BAUD_57600 57600
20#define UART16550_BAUD_115200 115200
21
22#define UART16550_PARITY_NONE 0
23#define UART16550_PARITY_ODD 0x08
24#define UART16550_PARITY_EVEN 0x18
25#define UART16550_PARITY_MARK 0x28
26#define UART16550_PARITY_SPACE 0x38
27
28#define UART16550_DATA_5BIT 0x0
29#define UART16550_DATA_6BIT 0x1
30#define UART16550_DATA_7BIT 0x2
31#define UART16550_DATA_8BIT 0x3
32
33#define UART16550_STOP_1BIT 0x0
34#define UART16550_STOP_2BIT 0x4
35
36/* ----------------------------------------------------- */
37
38/* === CONFIG === */
39
40/* [jsun] we use the second serial port for kdb */
41#define BASE OCELOT_SERIAL1_BASE
42#define MAX_BAUD OCELOT_BASE_BAUD
43
44/* === END OF CONFIG === */
45
46#define REG_OFFSET 4
47
48/* register offset */
49#define OFS_RCV_BUFFER 0
50#define OFS_TRANS_HOLD 0
51#define OFS_SEND_BUFFER 0
52#define OFS_INTR_ENABLE (1*REG_OFFSET)
53#define OFS_INTR_ID (2*REG_OFFSET)
54#define OFS_DATA_FORMAT (3*REG_OFFSET)
55#define OFS_LINE_CONTROL (3*REG_OFFSET)
56#define OFS_MODEM_CONTROL (4*REG_OFFSET)
57#define OFS_RS232_OUTPUT (4*REG_OFFSET)
58#define OFS_LINE_STATUS (5*REG_OFFSET)
59#define OFS_MODEM_STATUS (6*REG_OFFSET)
60#define OFS_RS232_INPUT (6*REG_OFFSET)
61#define OFS_SCRATCH_PAD (7*REG_OFFSET)
62
63#define OFS_DIVISOR_LSB (0*REG_OFFSET)
64#define OFS_DIVISOR_MSB (1*REG_OFFSET)
65
66
67/* memory-mapped read/write of the port */
68#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
69#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
70
71void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
72{
73 /* disable interrupts */
74 UART16550_WRITE(OFS_INTR_ENABLE, 0);
75
76 /* set up buad rate */
77 {
78 uint32 divisor;
79
80 /* set DIAB bit */
81 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
82
83 /* set divisor */
84 divisor = MAX_BAUD / baud;
85 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
86 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
87
88 /* clear DIAB bit */
89 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
90 }
91
92 /* set data format */
93 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
94}
95
96static int remoteDebugInitialized = 0;
97
98uint8 getDebugChar(void)
99{
100 if (!remoteDebugInitialized) {
101 remoteDebugInitialized = 1;
102 debugInit(UART16550_BAUD_38400,
103 UART16550_DATA_8BIT,
104 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
105 }
106
107 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
108 return UART16550_READ(OFS_RCV_BUFFER);
109}
110
111
112int putDebugChar(uint8 byte)
113{
114 if (!remoteDebugInitialized) {
115 remoteDebugInitialized = 1;
116 debugInit(UART16550_BAUD_38400,
117 UART16550_DATA_8BIT,
118 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
119 }
120
121 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
122 UART16550_WRITE(OFS_SEND_BUFFER, byte);
123 return 1;
124}
125
126#endif
diff --git a/arch/mips/momentum/ocelot_c/int-handler.S b/arch/mips/momentum/ocelot_c/int-handler.S
new file mode 100644
index 000000000000..2f2430648abc
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/int-handler.S
@@ -0,0 +1,102 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: jsun@mvista.com or jsun@junsun.net
7 *
8 * First-level interrupt dispatcher for Ocelot-CS board.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#include <asm/asm.h>
16#include <asm/mipsregs.h>
17#include <asm/addrspace.h>
18#include <asm/regdef.h>
19#include <asm/stackframe.h>
20#include "ocelot_c_fpga.h"
21
22/*
23 * First level interrupt dispatcher for Ocelot-CS board
24 */
25 .align 5
26 NESTED(ocelot_handle_int, PT_SIZE, sp)
27 SAVE_ALL
28 CLI
29 .set at
30 mfc0 t0, CP0_CAUSE
31 mfc0 t2, CP0_STATUS
32
33 and t0, t2
34
35 andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */
36 bnez t1, ll_sw0_irq
37 andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */
38 bnez t1, ll_sw1_irq
39 andi t1, t0, STATUSF_IP2 /* int0 hardware line */
40 bnez t1, ll_scsi_irq
41 andi t1, t0, STATUSF_IP3 /* int1 hardware line */
42 bnez t1, ll_uart_decode_irq
43 andi t1, t0, STATUSF_IP4 /* int2 hardware line */
44 bnez t1, ll_pmc_irq
45 andi t1, t0, STATUSF_IP5 /* int3 hardware line */
46 bnez t1, ll_cpci_decode_irq
47 andi t1, t0, STATUSF_IP6 /* int4 hardware line */
48 bnez t1, ll_mv64340_decode_irq
49 andi t1, t0, STATUSF_IP7 /* cpu timer */
50 bnez t1, ll_cputimer_irq
51
52 .set reorder
53
54 /* wrong alarm or masked ... */
55 j spurious_interrupt
56 nop
57 END(ocelot_handle_int)
58
59 .align 5
60ll_sw0_irq:
61 li a0, 0
62 move a1, sp
63 jal do_IRQ
64 j ret_from_irq
65ll_sw1_irq:
66 li a0, 1
67 move a1, sp
68 jal do_IRQ
69 j ret_from_irq
70ll_scsi_irq:
71 li a0, 2
72 move a1, sp
73 jal do_IRQ
74 j ret_from_irq
75
76ll_uart_decode_irq:
77 move a0, sp
78 jal ll_uart_irq
79 j ret_from_irq
80
81ll_pmc_irq:
82 li a0, 4
83 move a1, sp
84 jal do_IRQ
85 j ret_from_irq
86
87ll_cpci_decode_irq:
88 move a0, sp
89 jal ll_cpci_irq
90 j ret_from_irq
91
92ll_mv64340_decode_irq:
93 move a0, sp
94 jal ll_mv64340_irq
95 j ret_from_irq
96
97ll_cputimer_irq:
98 li a0, 7
99 move a1, sp
100 jal do_IRQ
101 j ret_from_irq
102
diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c
new file mode 100644
index 000000000000..300fe8e4fbe8
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/irq.c
@@ -0,0 +1,83 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 *
30 */
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/kernel_stat.h>
34#include <linux/module.h>
35#include <linux/signal.h>
36#include <linux/sched.h>
37#include <linux/types.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/timex.h>
41#include <linux/slab.h>
42#include <linux/random.h>
43#include <linux/bitops.h>
44#include <asm/bootinfo.h>
45#include <asm/io.h>
46#include <asm/irq_cpu.h>
47#include <asm/mipsregs.h>
48#include <asm/mv64340.h>
49#include <asm/system.h>
50
51extern asmlinkage void ocelot_handle_int(void);
52extern void uart_irq_init(void);
53extern void cpci_irq_init(void);
54
55static struct irqaction cascade_fpga = {
56 no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via FPGA", NULL, NULL
57};
58
59static struct irqaction cascade_mv64340 = {
60 no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
61};
62
63void __init arch_init_irq(void)
64{
65 /*
66 * Clear all of the interrupts while we change the able around a bit.
67 * int-handler is not on bootstrap
68 */
69 clear_c0_status(ST0_IM);
70
71 /* Sets the first-level interrupt dispatcher. */
72 set_except_vector(0, ocelot_handle_int);
73 mips_cpu_irq_init(0);
74
75 /* set up the cascading interrupts */
76 setup_irq(3, &cascade_fpga);
77 setup_irq(5, &cascade_fpga);
78 setup_irq(6, &cascade_mv64340);
79
80 mv64340_irq_init(16);
81 uart_irq_init();
82 cpci_irq_init();
83}
diff --git a/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h b/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
new file mode 100644
index 000000000000..a6cf7a7959b3
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
@@ -0,0 +1,60 @@
1/*
2 * Ocelot-C Board Register Definitions
3 *
4 * (C) 2002 Momentum Computer Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Louis Hamilton, Red Hat, Inc.
27 * hamilton@redhat.com [MIPS64 modifications]
28 */
29
30#ifndef __OCELOT_C_FPGA_H__
31#define __OCELOT_C_FPGA_H__
32
33#include <linux/config.h>
34
35#ifdef CONFIG_MIPS64
36#define OCELOT_C_CS0_ADDR (0xfffffffffc000000)
37#else
38#define OCELOT_C_CS0_ADDR (0xfc000000)
39#endif
40
41#define OCELOT_C_REG_BOARDREV 0x0
42#define OCELOT_C_REG_FPGA_REV 0x1
43#define OCELOT_C_REG_FPGA_TYPE 0x2
44#define OCELOT_C_REG_RESET_STATUS 0x3
45#define OCELOT_C_REG_BOARD_STATUS 0x4
46#define OCELOT_C_REG_CPCI_ID 0x5
47#define OCELOT_C_REG_SET 0x6
48#define OCELOT_C_REG_CLR 0x7
49#define OCELOT_C_REG_EEPROM_MODE 0x9
50#define OCELOT_C_REG_INTMASK 0xa
51#define OCELOT_C_REG_INTSTAT 0xb
52#define OCELOT_C_REG_UART_INTMASK 0xc
53#define OCELOT_C_REG_UART_INTSTAT 0xd
54#define OCELOT_C_REG_INTSET 0xe
55#define OCELOT_C_REG_INTCLR 0xf
56
57#define OCELOT_FPGA_WRITE(x, y) writeb(x, OCELOT_C_CS0_ADDR + OCELOT_C_REG_##y)
58#define OCELOT_FPGA_READ(x) readb(OCELOT_C_CS0_ADDR + OCELOT_C_REG_##x)
59
60#endif
diff --git a/arch/mips/momentum/ocelot_c/prom.c b/arch/mips/momentum/ocelot_c/prom.c
new file mode 100644
index 000000000000..49ac302d8901
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/prom.c
@@ -0,0 +1,243 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Louis Hamilton, Red Hat, Inc.
6 * hamilton@redhat.com [MIPS64 modifications]
7 *
8 * Based on Ocelot Linux port, which is
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: jsun@mvista.com or jsun@junsun.net
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#include <linux/config.h>
18#include <linux/init.h>
19#include <linux/mm.h>
20#include <linux/sched.h>
21#include <linux/bootmem.h>
22
23#include <asm/addrspace.h>
24#include <asm/bootinfo.h>
25#include <asm/mv64340.h>
26#include <asm/pmon.h>
27
28#include "ocelot_c_fpga.h"
29
30struct callvectors* debug_vectors;
31
32extern unsigned long marvell_base;
33extern unsigned long cpu_clock;
34
35#ifdef CONFIG_MV643XX_ETH
36extern unsigned char prom_mac_addr_base[6];
37#endif
38
39const char *get_system_type(void)
40{
41#ifdef CONFIG_CPU_SR71000
42 return "Momentum Ocelot-CS";
43#else
44 return "Momentum Ocelot-C";
45#endif
46}
47
48#ifdef CONFIG_MV643XX_ETH
49static void burn_clocks(void)
50{
51 int i;
52
53 /* this loop should burn at least 1us -- this should be plenty */
54 for (i = 0; i < 0x10000; i++)
55 ;
56}
57
58static u8 exchange_bit(u8 val, u8 cs)
59{
60 /* place the data */
61 OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
62 burn_clocks();
63
64 /* turn the clock on */
65 OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
66 burn_clocks();
67
68 /* turn the clock off and read-strobe */
69 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
70
71 /* return the data */
72 return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
73}
74
75void get_mac(char dest[6])
76{
77 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
78 int i,j;
79
80 for (i = 0; i < 12; i++)
81 exchange_bit(read_opcode[i], 1);
82
83 for (j = 0; j < 6; j++) {
84 dest[j] = 0;
85 for (i = 0; i < 8; i++) {
86 dest[j] <<= 1;
87 dest[j] |= exchange_bit(0, 1);
88 }
89 }
90
91 /* turn off CS */
92 exchange_bit(0,0);
93}
94#endif
95
96
97#ifdef CONFIG_MIPS64
98
99unsigned long signext(unsigned long addr)
100{
101 addr &= 0xffffffff;
102 return (unsigned long)((int)addr);
103}
104
105void *get_arg(unsigned long args, int arc)
106{
107 unsigned long ul;
108 unsigned char *puc, uc;
109
110 args += (arc * 4);
111 ul = (unsigned long)signext(args);
112 puc = (unsigned char *)ul;
113 if (puc == 0)
114 return (void *)0;
115
116#ifdef CONFIG_CPU_LITTLE_ENDIAN
117 uc = *puc++;
118 ul = (unsigned long)uc;
119 uc = *puc++;
120 ul |= (((unsigned long)uc) << 8);
121 uc = *puc++;
122 ul |= (((unsigned long)uc) << 16);
123 uc = *puc++;
124 ul |= (((unsigned long)uc) << 24);
125#else /* CONFIG_CPU_LITTLE_ENDIAN */
126 uc = *puc++;
127 ul = ((unsigned long)uc) << 24;
128 uc = *puc++;
129 ul |= (((unsigned long)uc) << 16);
130 uc = *puc++;
131 ul |= (((unsigned long)uc) << 8);
132 uc = *puc++;
133 ul |= ((unsigned long)uc);
134#endif /* CONFIG_CPU_LITTLE_ENDIAN */
135 ul = signext(ul);
136 return (void *)ul;
137}
138
139char *arg64(unsigned long addrin, int arg_index)
140{
141 unsigned long args;
142 char *p;
143 args = signext(addrin);
144 p = (char *)get_arg(args, arg_index);
145 return p;
146}
147#endif /* CONFIG_MIPS64 */
148
149
150void __init prom_init(void)
151{
152 int argc = fw_arg0;
153 char **arg = (char **) fw_arg1;
154 char **env = (char **) fw_arg2;
155 struct callvectors *cv = (struct callvectors *) fw_arg3;
156 int i;
157
158#ifdef CONFIG_MIPS64
159 char *ptr;
160
161 printk("prom_init - MIPS64\n");
162 /* save the PROM vectors for debugging use */
163 debug_vectors = (struct callvectors *)signext((unsigned long)cv);
164
165 /* arg[0] is "g", the rest is boot parameters */
166 arcs_cmdline[0] = '\0';
167
168 for (i = 1; i < argc; i++) {
169 ptr = (char *)arg64((unsigned long)arg, i);
170 if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
171 sizeof(arcs_cmdline))
172 break;
173 strcat(arcs_cmdline, ptr);
174 strcat(arcs_cmdline, " ");
175 }
176 i = 0;
177 while (1) {
178 ptr = (char *)arg64((unsigned long)env, i);
179 if (! ptr)
180 break;
181
182 if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
183 marvell_base = simple_strtol(ptr + strlen("gtbase="),
184 NULL, 16);
185
186 if ((marvell_base & 0xffffffff00000000) == 0)
187 marvell_base |= 0xffffffff00000000;
188
189 printk("marvell_base set to 0x%016lx\n", marvell_base);
190 }
191 if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
192 cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
193 NULL, 10);
194 printk("cpu_clock set to %d\n", cpu_clock);
195 }
196 i++;
197 }
198 printk("arcs_cmdline: %s\n", arcs_cmdline);
199
200#else /* CONFIG_MIPS64 */
201 /* save the PROM vectors for debugging use */
202 debug_vectors = cv;
203
204 /* arg[0] is "g", the rest is boot parameters */
205 arcs_cmdline[0] = '\0';
206 for (i = 1; i < argc; i++) {
207 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
208 >= sizeof(arcs_cmdline))
209 break;
210 strcat(arcs_cmdline, arg[i]);
211 strcat(arcs_cmdline, " ");
212 }
213
214 while (*env) {
215 if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
216 marvell_base = simple_strtol(*env + strlen("gtbase="),
217 NULL, 16);
218 }
219 if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
220 cpu_clock = simple_strtol(*env + strlen("cpuclock="),
221 NULL, 10);
222 }
223 env++;
224 }
225#endif /* CONFIG_MIPS64 */
226
227 mips_machgroup = MACH_GROUP_MOMENCO;
228 mips_machtype = MACH_MOMENCO_OCELOT_C;
229
230#ifdef CONFIG_MV643XX_ETH
231 /* get the base MAC address for on-board ethernet ports */
232 get_mac(prom_mac_addr_base);
233#endif
234
235#ifndef CONFIG_MIPS64
236 debug_vectors->printf("Booting Linux kernel...\n");
237#endif
238}
239
240unsigned long __init prom_free_prom_memory(void)
241{
242 return 0;
243}
diff --git a/arch/mips/momentum/ocelot_c/reset.c b/arch/mips/momentum/ocelot_c/reset.c
new file mode 100644
index 000000000000..1f2b4263cc8c
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/reset.c
@@ -0,0 +1,59 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 * Copyright (C) 2002 Momentum Computer Inc.
12 * Author: Matthew Dharm <mdharm@momenco.com>
13 *
14 * Louis Hamilton, Red Hat, Inc.
15 * hamilton@redhat.com [MIPS64 modifications]
16 */
17#include <linux/config.h>
18#include <linux/sched.h>
19#include <linux/mm.h>
20#include <asm/io.h>
21#include <asm/pgtable.h>
22#include <asm/processor.h>
23#include <asm/reboot.h>
24#include <asm/system.h>
25#include <linux/delay.h>
26
27void momenco_ocelot_restart(char *command)
28{
29 /* base address of timekeeper portion of part */
30 void *nvram = (void *)
31#ifdef CONFIG_MIPS64
32 0xfffffffffc807000;
33#else
34 0xfc807000;
35#endif
36
37 /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
38 writeb(0x84, nvram + 0xff7);
39
40 /* wait for the watchdog to go off */
41 mdelay(100+(1000/16));
42
43 /* if the watchdog fails for some reason, let people know */
44 printk(KERN_NOTICE "Watchdog reset failed\n");
45}
46
47void momenco_ocelot_halt(void)
48{
49 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
50 while (1)
51 __asm__(".set\tmips3\n\t"
52 "wait\n\t"
53 ".set\tmips0");
54}
55
56void momenco_ocelot_power_off(void)
57{
58 momenco_ocelot_halt();
59}
diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c
new file mode 100644
index 000000000000..021c00e3c07c
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/setup.c
@@ -0,0 +1,363 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Ocelot-C and -CS board dependent boot routines
4 *
5 * Copyright (C) 1996, 1997, 2001 Ralf Baechle
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
9 *
10 * Author: Matthew Dharm, Momentum Computer
11 * mdharm@momenco.com
12 *
13 * Louis Hamilton, Red Hat, Inc.
14 * hamilton@redhat.com [MIPS64 modifications]
15 *
16 * Author: RidgeRun, Inc.
17 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
18 *
19 * Copyright 2001 MontaVista Software Inc.
20 * Author: jsun@mvista.com or jsun@junsun.net
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License as published by the
24 * Free Software Foundation; either version 2 of the License, or (at your
25 * option) any later version.
26 *
27 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
30 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
33 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * You should have received a copy of the GNU General Public License along
39 * with this program; if not, write to the Free Software Foundation, Inc.,
40 * 675 Mass Ave, Cambridge, MA 02139, USA.
41 *
42 */
43#include <linux/config.h>
44#include <linux/bcd.h>
45#include <linux/init.h>
46#include <linux/kernel.h>
47#include <linux/types.h>
48#include <linux/mm.h>
49#include <linux/swap.h>
50#include <linux/ioport.h>
51#include <linux/sched.h>
52#include <linux/interrupt.h>
53#include <linux/pci.h>
54#include <linux/timex.h>
55#include <linux/vmalloc.h>
56#include <asm/time.h>
57#include <asm/bootinfo.h>
58#include <asm/page.h>
59#include <asm/io.h>
60#include <asm/irq.h>
61#include <asm/pci.h>
62#include <asm/processor.h>
63#include <asm/ptrace.h>
64#include <asm/reboot.h>
65#include <linux/bootmem.h>
66#include <linux/blkdev.h>
67#include <asm/mv64340.h>
68#include "ocelot_c_fpga.h"
69
70unsigned long marvell_base;
71extern unsigned long mv64340_sram_base;
72unsigned long cpu_clock;
73
74/* These functions are used for rebooting or halting the machine*/
75extern void momenco_ocelot_restart(char *command);
76extern void momenco_ocelot_halt(void);
77extern void momenco_ocelot_power_off(void);
78
79void momenco_time_init(void);
80
81static char reset_reason;
82
83void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask);
84
85static unsigned long ENTRYLO(unsigned long paddr)
86{
87 return ((paddr & PAGE_MASK) |
88 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
89 _CACHE_UNCACHED)) >> 6;
90}
91
92/* setup code for a handoff from a version 2 PMON 2000 PROM */
93void PMON_v2_setup(void)
94{
95 /* Some wired TLB entries for the MV64340 and perhiperals. The
96 MV64340 is going to be hit on every IRQ anyway - there's
97 absolutely no point in letting it be a random TLB entry, as
98 it'll just cause needless churning of the TLB. And we use
99 the other half for the serial port, which is just a PITA
100 otherwise :)
101
102 Device Physical Virtual
103 MV64340 Internal Regs 0xf4000000 0xf4000000
104 Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
105 NVRAM (CS1) 0xfc800000 0xfc800000
106 UARTs (CS2) 0xfd000000 0xfd000000
107 Internal SRAM 0xfe000000 0xfe000000
108 M-Systems DOC (CS3) 0xff000000 0xff000000
109 */
110 printk("PMON_v2_setup\n");
111
112#ifdef CONFIG_MIPS64
113 /* marvell and extra space */
114 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K);
115 /* fpga, rtc, and uart */
116 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfffffffffc000000, PM_16M);
117 /* m-sys and internal SRAM */
118 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
119
120 marvell_base = 0xfffffffff4000000;
121 mv64340_sram_base = 0xfffffffffe000000;
122#else
123 /* marvell and extra space */
124 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
125 /* fpga, rtc, and uart */
126 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M);
127 /* m-sys and internal SRAM */
128 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
129
130 marvell_base = 0xf4000000;
131 mv64340_sram_base = 0xfe000000;
132#endif
133}
134
135unsigned long m48t37y_get_time(void)
136{
137#ifdef CONFIG_MIPS64
138 unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000;
139#else
140 unsigned char* rtc_base = (unsigned char*)0xfc800000;
141#endif
142 unsigned int year, month, day, hour, min, sec;
143
144 /* stop the update */
145 rtc_base[0x7ff8] = 0x40;
146
147 year = BCD2BIN(rtc_base[0x7fff]);
148 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
149
150 month = BCD2BIN(rtc_base[0x7ffe]);
151
152 day = BCD2BIN(rtc_base[0x7ffd]);
153
154 hour = BCD2BIN(rtc_base[0x7ffb]);
155 min = BCD2BIN(rtc_base[0x7ffa]);
156 sec = BCD2BIN(rtc_base[0x7ff9]);
157
158 /* start the update */
159 rtc_base[0x7ff8] = 0x00;
160
161 return mktime(year, month, day, hour, min, sec);
162}
163
164int m48t37y_set_time(unsigned long sec)
165{
166#ifdef CONFIG_MIPS64
167 unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000;
168#else
169 unsigned char* rtc_base = (unsigned char*)0xfc800000;
170#endif
171 struct rtc_time tm;
172
173 /* convert to a more useful format -- note months count from 0 */
174 to_tm(sec, &tm);
175 tm.tm_mon += 1;
176
177 /* enable writing */
178 rtc_base[0x7ff8] = 0x80;
179
180 /* year */
181 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
182 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
183
184 /* month */
185 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
186
187 /* day */
188 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
189
190 /* hour/min/sec */
191 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
192 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
193 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
194
195 /* day of week -- not really used, but let's keep it up-to-date */
196 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
197
198 /* disable writing */
199 rtc_base[0x7ff8] = 0x00;
200
201 return 0;
202}
203
204void momenco_timer_setup(struct irqaction *irq)
205{
206 setup_irq(7, irq);
207}
208
209void momenco_time_init(void)
210{
211#ifdef CONFIG_CPU_SR71000
212 mips_hpt_frequency = cpu_clock;
213#elif defined(CONFIG_CPU_RM7000)
214 mips_hpt_frequency = cpu_clock / 2;
215#else
216#error Unknown CPU for this board
217#endif
218 printk("momenco_time_init cpu_clock=%d\n", cpu_clock);
219 board_timer_setup = momenco_timer_setup;
220
221 rtc_get_time = m48t37y_get_time;
222 rtc_set_time = m48t37y_set_time;
223}
224
225static void __init momenco_ocelot_c_setup(void)
226{
227 unsigned int tmpword;
228
229 board_time_init = momenco_time_init;
230
231 _machine_restart = momenco_ocelot_restart;
232 _machine_halt = momenco_ocelot_halt;
233 _machine_power_off = momenco_ocelot_power_off;
234
235 /*
236 * initrd_start = (ulong)ocelot_initrd_start;
237 * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
238 * initrd_below_start_ok = 1;
239 */
240
241 /* do handoff reconfiguration */
242 PMON_v2_setup();
243
244 /* shut down ethernet ports, just to be sure our memory doesn't get
245 * corrupted by random ethernet traffic.
246 */
247 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
248 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
249 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
250 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
251 do {}
252 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
253 do {}
254 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
255 do {}
256 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
257 do {}
258 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
259 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
260 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
261 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
262 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
263
264 /* Turn off the Bit-Error LED */
265 OCELOT_FPGA_WRITE(0x80, CLR);
266
267 tmpword = OCELOT_FPGA_READ(BOARDREV);
268#ifdef CONFIG_CPU_SR71000
269 if (tmpword < 26)
270 printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n",
271 'A'+tmpword);
272 else
273 printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n",
274 tmpword);
275#else
276 if (tmpword < 26)
277 printk("Momenco Ocelot-C: Board Assembly Rev. %c\n",
278 'A'+tmpword);
279 else
280 printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n",
281 tmpword);
282#endif
283
284 tmpword = OCELOT_FPGA_READ(FPGA_REV);
285 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
286 tmpword = OCELOT_FPGA_READ(RESET_STATUS);
287 printk("Reset reason: 0x%x\n", tmpword);
288 switch (tmpword) {
289 case 0x1:
290 printk(" - Power-up reset\n");
291 break;
292 case 0x2:
293 printk(" - Push-button reset\n");
294 break;
295 case 0x4:
296 printk(" - cPCI bus reset\n");
297 break;
298 case 0x8:
299 printk(" - Watchdog reset\n");
300 break;
301 case 0x10:
302 printk(" - Software reset\n");
303 break;
304 default:
305 printk(" - Unknown reset cause\n");
306 }
307 reset_reason = tmpword;
308 OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
309
310 tmpword = OCELOT_FPGA_READ(CPCI_ID);
311 printk("cPCI ID register: 0x%02x\n", tmpword);
312 printk(" - Slot number: %d\n", tmpword & 0x1f);
313 printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
314 printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
315
316 tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
317 printk("Board Status register: 0x%02x\n", tmpword);
318 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
319 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
320 printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
321 printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
322
323 switch(tmpword &3) {
324 case 3:
325 /* 512MiB */
326 add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM);
327 break;
328 case 2:
329 /* 256MiB */
330 add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
331 break;
332 case 1:
333 /* 128MiB */
334 add_memory_region(0x0, 0x80<<20, BOOT_MEM_RAM);
335 break;
336 case 0:
337 /* 1GiB -- needs CONFIG_HIGHMEM */
338 add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM);
339 break;
340 }
341}
342
343early_initcall(momenco_ocelot_c_setup);
344
345#ifndef CONFIG_MIPS64
346/* This needs to be one of the first initcalls, because no I/O port access
347 can work before this */
348static int io_base_ioremap(void)
349{
350 /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
351 void *io_remap_range = ioremap(0xc0000000, 0x30000000);
352
353 if (!io_remap_range) {
354 panic("Could not ioremap I/O port range");
355 }
356 printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range);
357 set_io_port_base(io_remap_range - 0xc0000000);
358
359 return 0;
360}
361
362module_init(io_base_ioremap);
363#endif
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
new file mode 100644
index 000000000000..ebe1507b17df
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/uart-irq.c
@@ -0,0 +1,147 @@
1/*
2 * Copyright 2002 Momentum Computer
3 * Author: mdharm@momenco.com
4 *
5 * arch/mips/momentum/ocelot_c/uart-irq.c
6 * Interrupt routines for UARTs. Interrupt numbers are assigned from
7 * 80 to 81 (2 interrupt sources).
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/kernel.h>
19#include <asm/ptrace.h>
20#include <linux/sched.h>
21#include <linux/kernel_stat.h>
22#include <asm/io.h>
23#include <asm/irq.h>
24#include "ocelot_c_fpga.h"
25
26static inline int ls1bit8(unsigned int x)
27{
28 int b = 7, s;
29
30 s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
31 s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
32 s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
33
34 return b;
35}
36
37/* mask off an interrupt -- 0 is enable, 1 is disable */
38static inline void mask_uart_irq(unsigned int irq)
39{
40 uint8_t value;
41
42 value = OCELOT_FPGA_READ(UART_INTMASK);
43 value |= 1 << (irq - 74);
44 OCELOT_FPGA_WRITE(value, UART_INTMASK);
45
46 /* read the value back to assure that it's really been written */
47 value = OCELOT_FPGA_READ(UART_INTMASK);
48}
49
50/* unmask an interrupt -- 0 is enable, 1 is disable */
51static inline void unmask_uart_irq(unsigned int irq)
52{
53 uint8_t value;
54
55 value = OCELOT_FPGA_READ(UART_INTMASK);
56 value &= ~(1 << (irq - 74));
57 OCELOT_FPGA_WRITE(value, UART_INTMASK);
58
59 /* read the value back to assure that it's really been written */
60 value = OCELOT_FPGA_READ(UART_INTMASK);
61}
62
63/*
64 * Enables the IRQ in the FPGA
65 */
66static void enable_uart_irq(unsigned int irq)
67{
68 unmask_uart_irq(irq);
69}
70
71/*
72 * Initialize the IRQ in the FPGA
73 */
74static unsigned int startup_uart_irq(unsigned int irq)
75{
76 unmask_uart_irq(irq);
77 return 0;
78}
79
80/*
81 * Disables the IRQ in the FPGA
82 */
83static void disable_uart_irq(unsigned int irq)
84{
85 mask_uart_irq(irq);
86}
87
88/*
89 * Masks and ACKs an IRQ
90 */
91static void mask_and_ack_uart_irq(unsigned int irq)
92{
93 mask_uart_irq(irq);
94}
95
96/*
97 * End IRQ processing
98 */
99static void end_uart_irq(unsigned int irq)
100{
101 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
102 unmask_uart_irq(irq);
103}
104
105/*
106 * Interrupt handler for interrupts coming from the FPGA chip.
107 */
108void ll_uart_irq(struct pt_regs *regs)
109{
110 unsigned int irq_src, irq_mask;
111
112 /* read the interrupt status registers */
113 irq_src = OCELOT_FPGA_READ(UART_INTSTAT);
114 irq_mask = OCELOT_FPGA_READ(UART_INTMASK);
115
116 /* mask for just the interrupts we want */
117 irq_src &= ~irq_mask;
118
119 do_IRQ(ls1bit8(irq_src) + 74, regs);
120}
121
122#define shutdown_uart_irq disable_uart_irq
123
124struct hw_interrupt_type uart_irq_type = {
125 "UART/FPGA",
126 startup_uart_irq,
127 shutdown_uart_irq,
128 enable_uart_irq,
129 disable_uart_irq,
130 mask_and_ack_uart_irq,
131 end_uart_irq,
132 NULL
133};
134
135void uart_irq_init(void)
136{
137 /* Reset irq handlers pointers to NULL */
138 irq_desc[80].status = IRQ_DISABLED;
139 irq_desc[80].action = 0;
140 irq_desc[80].depth = 2;
141 irq_desc[80].handler = &uart_irq_type;
142
143 irq_desc[81].status = IRQ_DISABLED;
144 irq_desc[81].action = 0;
145 irq_desc[81].depth = 2;
146 irq_desc[81].handler = &uart_irq_type;
147}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 23:07:07 -0500