diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2006-04-03 12:56:36 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2006-04-18 22:14:21 -0400 |
commit | e4ac58afdfac792c0583af30dbd9eae53e24c78b (patch) | |
tree | 7517bef2c515fc630e4d3d238867b91cde96f558 /arch/mips/momentum/ocelot_c/irq.c | |
parent | d35d473c25d43d7db3e5e18b66d558d2a631cca8 (diff) |
[MIPS] Rewrite all the assembler interrupt handlers to C.
Saves like 1,600 lines of code, is way easier to debug, compilers
frequently do a better job than the cut and paste type of handlers many
boards had. And finally having all the stuff done in a single place
also means alot of bug potencial for the MT ASE is gone.
The only surviving handler in assembler is the DECstation one; I hope
Maciej will rewrite it.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/momentum/ocelot_c/irq.c')
-rw-r--r-- | arch/mips/momentum/ocelot_c/irq.c | 30 |
1 files changed, 27 insertions, 3 deletions
diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c index a5764bc20e36..86f61ce59e53 100644 --- a/arch/mips/momentum/ocelot_c/irq.c +++ b/arch/mips/momentum/ocelot_c/irq.c | |||
@@ -48,7 +48,6 @@ | |||
48 | #include <asm/mipsregs.h> | 48 | #include <asm/mipsregs.h> |
49 | #include <asm/system.h> | 49 | #include <asm/system.h> |
50 | 50 | ||
51 | extern asmlinkage void ocelot_handle_int(void); | ||
52 | extern void uart_irq_init(void); | 51 | extern void uart_irq_init(void); |
53 | extern void cpci_irq_init(void); | 52 | extern void cpci_irq_init(void); |
54 | 53 | ||
@@ -60,6 +59,33 @@ static struct irqaction cascade_mv64340 = { | |||
60 | no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL | 59 | no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL |
61 | }; | 60 | }; |
62 | 61 | ||
62 | extern void ll_uart_irq(struct pt_regs *regs); | ||
63 | extern void ll_cpci_irq(struct pt_regs *regs); | ||
64 | |||
65 | asmlinkage void plat_irq_dispatch(struct pt_regs *regs) | ||
66 | { | ||
67 | unsigned int pending = read_c0_cause() & read_c0_status(); | ||
68 | |||
69 | if (pending & STATUSF_IP0) | ||
70 | do_IRQ(0, regs); | ||
71 | else if (pending & STATUSF_IP1) | ||
72 | do_IRQ(1, regs); | ||
73 | else if (pending & STATUSF_IP2) | ||
74 | do_IRQ(2, regs); | ||
75 | else if (pending & STATUSF_IP3) | ||
76 | ll_uart_irq(regs); | ||
77 | else if (pending & STATUSF_IP4) | ||
78 | do_IRQ(4, regs); | ||
79 | else if (pending & STATUSF_IP5) | ||
80 | ll_cpci_irq(regs); | ||
81 | else if (pending & STATUSF_IP6) | ||
82 | ll_mv64340_irq(regs); | ||
83 | else if (pending & STATUSF_IP7) | ||
84 | do_IRQ(7, regs); | ||
85 | else | ||
86 | spurious_interrupt(regs); | ||
87 | } | ||
88 | |||
63 | void __init arch_init_irq(void) | 89 | void __init arch_init_irq(void) |
64 | { | 90 | { |
65 | /* | 91 | /* |
@@ -68,8 +94,6 @@ void __init arch_init_irq(void) | |||
68 | */ | 94 | */ |
69 | clear_c0_status(ST0_IM); | 95 | clear_c0_status(ST0_IM); |
70 | 96 | ||
71 | /* Sets the first-level interrupt dispatcher. */ | ||
72 | set_except_vector(0, ocelot_handle_int); | ||
73 | mips_cpu_irq_init(0); | 97 | mips_cpu_irq_init(0); |
74 | 98 | ||
75 | /* set up the cascading interrupts */ | 99 | /* set up the cascading interrupts */ |