diff options
author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2007-01-07 12:14:29 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-02-06 11:53:08 -0500 |
commit | 97dcb82de6cc99a5669eb8e342efc24cceb1e77e (patch) | |
tree | e195fd57deda8d38652c746c04a7c374cdf951a0 /arch/mips/momentum/ocelot_3 | |
parent | b6ec8f069bf202d2bd888aa9137b2cc3aad4c573 (diff) |
[MIPS] Define MIPS_CPU_IRQ_BASE in generic header
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.
A good side effect is removing some dependencies to MALTA in generic
SMTC code.
Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
Testing this patch on those platforms is greatly appreciated. Thank
you.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/momentum/ocelot_3')
-rw-r--r-- | arch/mips/momentum/ocelot_3/irq.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/momentum/ocelot_3/irq.c b/arch/mips/momentum/ocelot_3/irq.c index cea0e5deb80e..3862d1d1add4 100644 --- a/arch/mips/momentum/ocelot_3/irq.c +++ b/arch/mips/momentum/ocelot_3/irq.c | |||
@@ -65,7 +65,7 @@ void __init arch_init_irq(void) | |||
65 | */ | 65 | */ |
66 | clear_c0_status(ST0_IM | ST0_BEV); | 66 | clear_c0_status(ST0_IM | ST0_BEV); |
67 | 67 | ||
68 | rm7k_cpu_irq_init(8); | 68 | rm7k_cpu_irq_init(); |
69 | 69 | ||
70 | /* set up the cascading interrupts */ | 70 | /* set up the cascading interrupts */ |
71 | setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */ | 71 | setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */ |