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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/momentum/ocelot_3
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/mips/momentum/ocelot_3')
-rw-r--r--arch/mips/momentum/ocelot_3/Makefile8
-rw-r--r--arch/mips/momentum/ocelot_3/int-handler.S137
-rw-r--r--arch/mips/momentum/ocelot_3/irq.c81
-rw-r--r--arch/mips/momentum/ocelot_3/ocelot_3_fpga.h57
-rw-r--r--arch/mips/momentum/ocelot_3/prom.c248
-rw-r--r--arch/mips/momentum/ocelot_3/reset.c59
-rw-r--r--arch/mips/momentum/ocelot_3/setup.c398
7 files changed, 988 insertions, 0 deletions
diff --git a/arch/mips/momentum/ocelot_3/Makefile b/arch/mips/momentum/ocelot_3/Makefile
new file mode 100644
index 000000000000..aab8fd89f830
--- /dev/null
+++ b/arch/mips/momentum/ocelot_3/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for Momentum Computer's Ocelot-3 board.
3#
4# Note! Dependencies are done automagically by 'make dep', which also
5# removes any old dependencies. DON'T put your own dependencies here
6# unless it's something special (ie not a .c file).
7#
8obj-y += int-handler.o irq.o prom.o reset.o setup.o
diff --git a/arch/mips/momentum/ocelot_3/int-handler.S b/arch/mips/momentum/ocelot_3/int-handler.S
new file mode 100644
index 000000000000..4522f09ed769
--- /dev/null
+++ b/arch/mips/momentum/ocelot_3/int-handler.S
@@ -0,0 +1,137 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: jsun@mvista.com or jsun@junsun.net
7 *
8 * Copyright 2004 PMC-Sierra
9 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
10 *
11 * Copyright (C) 2004 MontaVista Software Inc.
12 * Author: Manish Lachwani, mlachwani@mvista.com
13 *
14 * First-level interrupt dispatcher for Ocelot-3 board.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 */
21#include <asm/asm.h>
22#include <asm/mipsregs.h>
23#include <asm/addrspace.h>
24#include <asm/regdef.h>
25#include <asm/stackframe.h>
26
27/*
28 * First level interrupt dispatcher for Ocelot-3 board
29 */
30 .align 5
31 NESTED(ocelot3_handle_int, PT_SIZE, sp)
32 SAVE_ALL
33 CLI
34 .set at
35
36 mfc0 t0, CP0_CAUSE
37 mfc0 t2, CP0_STATUS
38
39 and t0, t2
40
41 andi t1, t0, STATUSF_IP0 /* sw0 software interrupt (IRQ0) */
42 bnez t1, ll_sw0_irq
43
44 andi t1, t0, STATUSF_IP1 /* sw1 software interrupt (IRQ1) */
45 bnez t1, ll_sw1_irq
46
47 andi t1, t0, STATUSF_IP2 /* int0 hardware line (IRQ2) */
48 bnez t1, ll_pci0slot1_irq
49
50 andi t1, t0, STATUSF_IP3 /* int1 hardware line (IRQ3) */
51 bnez t1, ll_pci0slot2_irq
52
53 andi t1, t0, STATUSF_IP4 /* int2 hardware line (IRQ4) */
54 bnez t1, ll_pci1slot1_irq
55
56 andi t1, t0, STATUSF_IP5 /* int3 hardware line (IRQ5) */
57 bnez t1, ll_pci1slot2_irq
58
59 andi t1, t0, STATUSF_IP6 /* int4 hardware line (IRQ6) */
60 bnez t1, ll_uart_irq
61
62 andi t1, t0, STATUSF_IP7 /* cpu timer (IRQ7) */
63 bnez t1, ll_cputimer_irq
64
65 /* now look at extended interrupts */
66 mfc0 t0, CP0_CAUSE
67 cfc0 t1, CP0_S1_INTCONTROL
68
69 /* shift the mask 8 bits left to line up the bits */
70 sll t2, t1, 8
71
72 and t0, t2
73 srl t0, t0, 16
74
75 andi t1, t0, STATUSF_IP8 /* int6 hardware line (IRQ9) */
76 bnez t1, ll_mv64340_decode_irq
77
78 .set reorder
79
80 /* wrong alarm or masked ... */
81 j spurious_interrupt
82 nop
83 END(ocelot3_handle_int)
84
85 .align 5
86ll_sw0_irq:
87 li a0, 0 /* IRQ 1 */
88 move a1, sp
89 jal do_IRQ
90 j ret_from_irq
91ll_sw1_irq:
92 li a0, 1 /* IRQ 2 */
93 move a1, sp
94 jal do_IRQ
95 j ret_from_irq
96
97ll_pci0slot1_irq:
98 li a0, 2 /* IRQ 3 */
99 move a1, sp
100 jal do_IRQ
101 j ret_from_irq
102
103ll_pci0slot2_irq:
104 li a0, 3 /* IRQ 4 */
105 move a1, sp
106 jal do_IRQ
107 j ret_from_irq
108
109ll_pci1slot1_irq:
110 li a0, 4 /* IRQ 5 */
111 move a1, sp
112 jal do_IRQ
113 j ret_from_irq
114
115ll_pci1slot2_irq:
116 li a0, 5 /* IRQ 6 */
117 move a1, sp
118 jal do_IRQ
119 j ret_from_irq
120
121ll_uart_irq:
122 li a0, 6 /* IRQ 7 */
123 move a1, sp
124 jal do_IRQ
125 j ret_from_irq
126
127ll_cputimer_irq:
128 li a0, 7 /* IRQ 8 */
129 move a1, sp
130 jal do_IRQ
131 j ret_from_irq
132
133ll_mv64340_decode_irq:
134 move a0, sp
135 jal ll_mv64340_irq
136 j ret_from_irq
137
diff --git a/arch/mips/momentum/ocelot_3/irq.c b/arch/mips/momentum/ocelot_3/irq.c
new file mode 100644
index 000000000000..42464dbd4ad2
--- /dev/null
+++ b/arch/mips/momentum/ocelot_3/irq.c
@@ -0,0 +1,81 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
9 *
10 * Copyright 2004 PMC-Sierra
11 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 *
33 * Copyright (C) 2004 MontaVista Software Inc.
34 * Author: Manish Lachwani, mlachwani@mvista.com
35 *
36 */
37#include <linux/errno.h>
38#include <linux/init.h>
39#include <linux/kernel_stat.h>
40#include <linux/module.h>
41#include <linux/signal.h>
42#include <linux/sched.h>
43#include <linux/types.h>
44#include <linux/interrupt.h>
45#include <linux/ioport.h>
46#include <linux/timex.h>
47#include <linux/slab.h>
48#include <linux/random.h>
49#include <asm/bitops.h>
50#include <asm/bootinfo.h>
51#include <asm/io.h>
52#include <asm/irq.h>
53#include <asm/mipsregs.h>
54#include <asm/system.h>
55
56extern asmlinkage void ocelot3_handle_int(void);
57
58static struct irqaction cascade_mv64340 = {
59 no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
60};
61
62void __init arch_init_irq(void)
63{
64 /*
65 * Clear all of the interrupts while we change the able around a bit.
66 * int-handler is not on bootstrap
67 */
68 clear_c0_status(ST0_IM | ST0_BEV);
69
70 /* Sets the first-level interrupt dispatcher. */
71 set_except_vector(0, ocelot3_handle_int);
72 mips_cpu_irq_init(0);
73 rm7k_cpu_irq_init(8);
74
75 /* set up the cascading interrupts */
76 setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */
77 mv64340_irq_init(16);
78
79 set_c0_status(ST0_IM); /* IE in the status register */
80
81}
diff --git a/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h b/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h
new file mode 100644
index 000000000000..227e429fe720
--- /dev/null
+++ b/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h
@@ -0,0 +1,57 @@
1/*
2 * Ocelot-3 Board Register Definitions
3 *
4 * (C) 2002 Momentum Computer Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Louis Hamilton, Red Hat, Inc.
27 * hamilton@redhat.com [MIPS64 modifications]
28 *
29 * Copyright (C) 2004 MontaVista Software Inc.
30 * Author: Manish Lachwani, mlachwani@mvista.com
31 */
32
33#ifndef __OCELOT_3_FPGA_H__
34#define __OCELOT_3_FPGA_H__
35
36#define OCELOT_3_REG_BOARDREV 0x0
37#define OCELOT_3_REG_FPGA_REV 0x1
38#define OCELOT_3_REG_FPGA_TYPE 0x2
39#define OCELOT_3_REG_RESET_STATUS 0x3
40#define OCELOT_3_REG_BOARD_STATUS 0x4
41#define OCELOT_3_REG_CPCI_ID 0x5
42#define OCELOT_3_REG_SET 0x6
43#define OCELOT_3_REG_CLR 0x7
44#define OCELOT_3_REG_EEPROM_MODE 0x9
45#define OCELOT_3_REG_INTMASK 0xa
46#define OCELOT_3_REG_INTSTAT 0xb
47#define OCELOT_3_REG_UART_INTMASK 0xc
48#define OCELOT_3_REG_UART_INTSTAT 0xd
49#define OCELOT_3_REG_INTSET 0xe
50#define OCELOT_3_REG_INTCLR 0xf
51
52extern unsigned long ocelot_fpga_base;
53
54#define OCELOT_FPGA_WRITE(x, y) writeb(x, ocelot_fpga_base + OCELOT_3_REG_##y)
55#define OCELOT_FPGA_READ(x) readb(ocelot_fpga_base + OCELOT_3_REG_##x)
56
57#endif
diff --git a/arch/mips/momentum/ocelot_3/prom.c b/arch/mips/momentum/ocelot_3/prom.c
new file mode 100644
index 000000000000..89c17a0c0bed
--- /dev/null
+++ b/arch/mips/momentum/ocelot_3/prom.c
@@ -0,0 +1,248 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Louis Hamilton, Red Hat, Inc.
6 * hamilton@redhat.com [MIPS64 modifications]
7 *
8 * Copyright 2004 PMC-Sierra
9 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
10 *
11 * Based on Ocelot Linux port, which is
12 * Copyright 2001 MontaVista Software Inc.
13 * Author: jsun@mvista.com or jsun@junsun.net
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Copyright (C) 2004 MontaVista Software Inc.
21 * Author: Manish Lachwani, mlachwani@mvista.com
22 *
23 */
24#include <linux/config.h>
25#include <linux/init.h>
26#include <linux/bootmem.h>
27#include <linux/mv643xx.h>
28
29#include <asm/addrspace.h>
30#include <asm/bootinfo.h>
31#include <asm/pmon.h>
32#include "ocelot_3_fpga.h"
33
34struct callvectors* debug_vectors;
35extern unsigned long marvell_base;
36extern unsigned long cpu_clock;
37
38#ifdef CONFIG_MV643XX_ETH
39extern unsigned char prom_mac_addr_base[6];
40#endif
41
42const char *get_system_type(void)
43{
44 return "Momentum Ocelot-3";
45}
46
47#ifdef CONFIG_MV643XX_ETH
48void burn_clocks(void)
49{
50 int i;
51
52 /* this loop should burn at least 1us -- this should be plenty */
53 for (i = 0; i < 0x10000; i++)
54 ;
55}
56
57u8 exchange_bit(u8 val, u8 cs)
58{
59 /* place the data */
60 OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
61 burn_clocks();
62
63 /* turn the clock on */
64 OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
65 burn_clocks();
66
67 /* turn the clock off and read-strobe */
68 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
69
70 /* return the data */
71 return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
72}
73
74void get_mac(char dest[6])
75{
76 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
77 int i,j;
78
79 for (i = 0; i < 12; i++)
80 exchange_bit(read_opcode[i], 1);
81
82 for (j = 0; j < 6; j++) {
83 dest[j] = 0;
84 for (i = 0; i < 8; i++) {
85 dest[j] <<= 1;
86 dest[j] |= exchange_bit(0, 1);
87 }
88 }
89
90 /* turn off CS */
91 exchange_bit(0,0);
92}
93#endif
94
95
96#ifdef CONFIG_MIPS64
97
98unsigned long signext(unsigned long addr)
99{
100 addr &= 0xffffffff;
101 return (unsigned long)((int)addr);
102}
103
104void *get_arg(unsigned long args, int arc)
105{
106 unsigned long ul;
107 unsigned char *puc, uc;
108
109 args += (arc * 4);
110 ul = (unsigned long)signext(args);
111 puc = (unsigned char *)ul;
112 if (puc == 0)
113 return (void *)0;
114
115#ifdef CONFIG_CPU_LITTLE_ENDIAN
116 uc = *puc++;
117 ul = (unsigned long)uc;
118 uc = *puc++;
119 ul |= (((unsigned long)uc) << 8);
120 uc = *puc++;
121 ul |= (((unsigned long)uc) << 16);
122 uc = *puc++;
123 ul |= (((unsigned long)uc) << 24);
124#else /* CONFIG_CPU_LITTLE_ENDIAN */
125 uc = *puc++;
126 ul = ((unsigned long)uc) << 24;
127 uc = *puc++;
128 ul |= (((unsigned long)uc) << 16);
129 uc = *puc++;
130 ul |= (((unsigned long)uc) << 8);
131 uc = *puc++;
132 ul |= ((unsigned long)uc);
133#endif /* CONFIG_CPU_LITTLE_ENDIAN */
134 ul = signext(ul);
135 return (void *)ul;
136}
137
138char *arg64(unsigned long addrin, int arg_index)
139{
140 unsigned long args;
141 char *p;
142
143 args = signext(addrin);
144 p = (char *)get_arg(args, arg_index);
145
146 return p;
147}
148#endif /* CONFIG_MIPS64 */
149
150void __init prom_init(void)
151{
152 int argc = fw_arg0;
153 char **arg = (char **) fw_arg1;
154 char **env = (char **) fw_arg2;
155 struct callvectors *cv = (struct callvectors *) fw_arg3;
156 int i;
157
158#ifdef CONFIG_MIPS64
159 char *ptr;
160 printk("prom_init - MIPS64\n");
161
162 /* save the PROM vectors for debugging use */
163 debug_vectors = (struct callvectors *)signext((unsigned long)cv);
164
165 /* arg[0] is "g", the rest is boot parameters */
166 arcs_cmdline[0] = '\0';
167
168 for (i = 1; i < argc; i++) {
169 ptr = (char *)arg64((unsigned long)arg, i);
170 if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
171 sizeof(arcs_cmdline))
172 break;
173 strcat(arcs_cmdline, ptr);
174 strcat(arcs_cmdline, " ");
175 }
176 i = 0;
177
178 while (1) {
179 ptr = (char *)arg64((unsigned long)env, i);
180 if (! ptr)
181 break;
182
183 if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
184 marvell_base = simple_strtol(ptr + strlen("gtbase="),
185 NULL, 16);
186
187 if ((marvell_base & 0xffffffff00000000) == 0)
188 marvell_base |= 0xffffffff00000000;
189
190 printk("marvell_base set to 0x%016lx\n", marvell_base);
191 }
192 if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
193 cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
194 NULL, 10);
195 printk("cpu_clock set to %d\n", cpu_clock);
196 }
197 i++;
198 }
199 printk("arcs_cmdline: %s\n", arcs_cmdline);
200
201#else /* CONFIG_MIPS64 */
202
203 /* save the PROM vectors for debugging use */
204 debug_vectors = cv;
205
206 /* arg[0] is "g", the rest is boot parameters */
207 arcs_cmdline[0] = '\0';
208 for (i = 1; i < argc; i++) {
209 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
210 >= sizeof(arcs_cmdline))
211 break;
212 strcat(arcs_cmdline, arg[i]);
213 strcat(arcs_cmdline, " ");
214 }
215
216 while (*env) {
217 if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
218 marvell_base = simple_strtol(*env + strlen("gtbase="),
219 NULL, 16);
220 }
221 if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
222 cpu_clock = simple_strtol(*env + strlen("cpuclock="),
223 NULL, 10);
224 }
225 env++;
226 }
227#endif /* CONFIG_MIPS64 */
228
229 mips_machgroup = MACH_GROUP_MOMENCO;
230 mips_machtype = MACH_MOMENCO_OCELOT_3;
231
232#ifdef CONFIG_MV643XX_ETH
233 /* get the base MAC address for on-board ethernet ports */
234 get_mac(prom_mac_addr_base);
235#endif
236
237#ifndef CONFIG_MIPS64
238 debug_vectors->printf("Booting Linux kernel...\n");
239#endif
240}
241
242void __init prom_free_prom_memory(void)
243{
244}
245
246void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
247{
248}
diff --git a/arch/mips/momentum/ocelot_3/reset.c b/arch/mips/momentum/ocelot_3/reset.c
new file mode 100644
index 000000000000..72b4423c0864
--- /dev/null
+++ b/arch/mips/momentum/ocelot_3/reset.c
@@ -0,0 +1,59 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 01, 05 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 * Copyright (C) 2002 Momentum Computer Inc.
12 * Author: Matthew Dharm <mdharm@momenco.com>
13 *
14 * Louis Hamilton, Red Hat, Inc.
15 * hamilton@redhat.com [MIPS64 modifications]
16 *
17 * Copyright 2004 PMC-Sierra
18 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
19 *
20 * Copyright (C) 2004 MontaVista Software Inc.
21 * Author: Manish Lachwani, mlachwani@mvista.com
22 */
23#include <linux/sched.h>
24#include <linux/mm.h>
25#include <linux/delay.h>
26#include <asm/io.h>
27#include <asm/pgtable.h>
28#include <asm/processor.h>
29#include <asm/reboot.h>
30#include <asm/system.h>
31
32void momenco_ocelot_restart(char *command)
33{
34 /* base address of timekeeper portion of part */
35 void *nvram = (void *) 0xfc807000L;
36
37 /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
38 writeb(0x84, nvram + 0xff7);
39
40 /* wait for the watchdog to go off */
41 mdelay(100+(1000/16));
42
43 /* if the watchdog fails for some reason, let people know */
44 printk(KERN_NOTICE "Watchdog reset failed\n");
45}
46
47void momenco_ocelot_halt(void)
48{
49 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
50 while (1)
51 __asm__(".set\tmips3\n\t"
52 "wait\n\t"
53 ".set\tmips0");
54}
55
56void momenco_ocelot_power_off(void)
57{
58 momenco_ocelot_halt();
59}
diff --git a/arch/mips/momentum/ocelot_3/setup.c b/arch/mips/momentum/ocelot_3/setup.c
new file mode 100644
index 000000000000..ce2efcbab7aa
--- /dev/null
+++ b/arch/mips/momentum/ocelot_3/setup.c
@@ -0,0 +1,398 @@
1/*
2 * setup.c
3 *
4 * BRIEF MODULE DESCRIPTION
5 * Momentum Computer Ocelot-3 board dependent boot routines
6 *
7 * Copyright (C) 1996, 1997, 01, 05 Ralf Baechle
8 * Copyright (C) 2000 RidgeRun, Inc.
9 * Copyright (C) 2001 Red Hat, Inc.
10 * Copyright (C) 2002 Momentum Computer
11 *
12 * Author: Matthew Dharm, Momentum Computer
13 * mdharm@momenco.com
14 *
15 * Louis Hamilton, Red Hat, Inc.
16 * hamilton@redhat.com [MIPS64 modifications]
17 *
18 * Author: RidgeRun, Inc.
19 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
20 *
21 * Copyright 2001 MontaVista Software Inc.
22 * Author: jsun@mvista.com or jsun@junsun.net
23 *
24 * Copyright 2004 PMC-Sierra
25 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
26 *
27 * Copyright (C) 2004 MontaVista Software Inc.
28 * Author: Manish Lachwani, mlachwani@mvista.com
29 *
30 * This program is free software; you can redistribute it and/or modify it
31 * under the terms of the GNU General Public License as published by the
32 * Free Software Foundation; either version 2 of the License, or (at your
33 * option) any later version.
34 *
35 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
36 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
37 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
38 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
40 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
41 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
42 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
44 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 * You should have received a copy of the GNU General Public License along
47 * with this program; if not, write to the Free Software Foundation, Inc.,
48 * 675 Mass Ave, Cambridge, MA 02139, USA.
49 */
50#include <linux/init.h>
51#include <linux/kernel.h>
52#include <linux/types.h>
53#include <linux/mc146818rtc.h>
54#include <linux/ioport.h>
55#include <linux/interrupt.h>
56#include <linux/pci.h>
57#include <linux/timex.h>
58#include <linux/bootmem.h>
59#include <linux/mv643xx.h>
60#include <asm/time.h>
61#include <asm/page.h>
62#include <asm/bootinfo.h>
63#include <asm/io.h>
64#include <asm/irq.h>
65#include <asm/pci.h>
66#include <asm/processor.h>
67#include <asm/ptrace.h>
68#include <asm/reboot.h>
69#include <asm/mc146818rtc.h>
70#include <asm/tlbflush.h>
71#include "ocelot_3_fpga.h"
72
73/* Marvell Discovery Register Base */
74unsigned long marvell_base = (signed)0xf4000000;
75
76/* CPU clock */
77unsigned long cpu_clock;
78
79/* RTC/NVRAM */
80unsigned char* rtc_base = (unsigned char*)(signed)0xfc800000;
81
82/* FPGA Base */
83unsigned long ocelot_fpga_base = (signed)0xfc000000;
84
85/* Serial base */
86unsigned long uart_base = (signed)0xfd000000;
87
88/*
89 * Marvell Discovery SRAM. This is one place where Ethernet
90 * Tx and Rx descriptors can be placed to improve performance
91 */
92extern unsigned long mv64340_sram_base;
93
94/* These functions are used for rebooting or halting the machine*/
95extern void momenco_ocelot_restart(char *command);
96extern void momenco_ocelot_halt(void);
97extern void momenco_ocelot_power_off(void);
98
99void momenco_time_init(void);
100static char reset_reason;
101
102void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
103 unsigned long entryhi, unsigned long pagemask);
104
105static inline unsigned long ENTRYLO(unsigned long paddr)
106{
107 return ((paddr & PAGE_MASK) |
108 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
109 _CACHE_UNCACHED)) >> 6;
110}
111
112void __init bus_error_init(void)
113{
114 /* nothing */
115}
116
117/*
118 * setup code for a handoff from a version 2 PMON 2000 PROM
119 */
120void setup_wired_tlb_entries(void)
121{
122 write_c0_wired(0);
123 local_flush_tlb_all();
124
125 /* marvell and extra space */
126 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), (signed)0xf4000000, PM_64K);
127
128 /* fpga, rtc, and uart */
129 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), (signed)0xfc000000, PM_16M);
130}
131
132#define CONV_BCD_TO_BIN(val) (((val) & 0xf) + (((val) >> 4) * 10))
133#define CONV_BIN_TO_BCD(val) (((val) % 10) + (((val) / 10) << 4))
134
135unsigned long m48t37y_get_time(void)
136{
137 unsigned int year, month, day, hour, min, sec;
138
139 /* stop the update */
140 rtc_base[0x7ff8] = 0x40;
141
142 year = CONV_BCD_TO_BIN(rtc_base[0x7fff]);
143 year += CONV_BCD_TO_BIN(rtc_base[0x7ff1]) * 100;
144
145 month = CONV_BCD_TO_BIN(rtc_base[0x7ffe]);
146
147 day = CONV_BCD_TO_BIN(rtc_base[0x7ffd]);
148
149 hour = CONV_BCD_TO_BIN(rtc_base[0x7ffb]);
150 min = CONV_BCD_TO_BIN(rtc_base[0x7ffa]);
151 sec = CONV_BCD_TO_BIN(rtc_base[0x7ff9]);
152
153 /* start the update */
154 rtc_base[0x7ff8] = 0x00;
155
156 return mktime(year, month, day, hour, min, sec);
157}
158
159int m48t37y_set_time(unsigned long sec)
160{
161 struct rtc_time tm;
162
163 /* convert to a more useful format -- note months count from 0 */
164 to_tm(sec, &tm);
165 tm.tm_mon += 1;
166
167 /* enable writing */
168 rtc_base[0x7ff8] = 0x80;
169
170 /* year */
171 rtc_base[0x7fff] = CONV_BIN_TO_BCD(tm.tm_year % 100);
172 rtc_base[0x7ff1] = CONV_BIN_TO_BCD(tm.tm_year / 100);
173
174 /* month */
175 rtc_base[0x7ffe] = CONV_BIN_TO_BCD(tm.tm_mon);
176
177 /* day */
178 rtc_base[0x7ffd] = CONV_BIN_TO_BCD(tm.tm_mday);
179
180 /* hour/min/sec */
181 rtc_base[0x7ffb] = CONV_BIN_TO_BCD(tm.tm_hour);
182 rtc_base[0x7ffa] = CONV_BIN_TO_BCD(tm.tm_min);
183 rtc_base[0x7ff9] = CONV_BIN_TO_BCD(tm.tm_sec);
184
185 /* day of week -- not really used, but let's keep it up-to-date */
186 rtc_base[0x7ffc] = CONV_BIN_TO_BCD(tm.tm_wday + 1);
187
188 /* disable writing */
189 rtc_base[0x7ff8] = 0x00;
190
191 return 0;
192}
193
194void momenco_timer_setup(struct irqaction *irq)
195{
196 setup_irq(7, irq); /* Timer interrupt, unmask status IM7 */
197}
198
199void momenco_time_init(void)
200{
201 setup_wired_tlb_entries();
202
203 /*
204 * Ocelot-3 board has been built with both
205 * the Rm7900 and the Rm7065C
206 */
207 mips_hpt_frequency = cpu_clock / 2;
208 board_timer_setup = momenco_timer_setup;
209
210 rtc_get_time = m48t37y_get_time;
211 rtc_set_time = m48t37y_set_time;
212}
213
214/*
215 * PCI Support for Ocelot-3
216 */
217
218/* Bus #0 IO and MEM space */
219#define OCELOT_3_PCI_IO_0_START 0xe0000000
220#define OCELOT_3_PCI_IO_0_SIZE 0x08000000
221#define OCELOT_3_PCI_MEM_0_START 0xc0000000
222#define OCELOT_3_PCI_MEM_0_SIZE 0x10000000
223
224/* Bus #1 IO and MEM space */
225#define OCELOT_3_PCI_IO_1_START 0xe8000000
226#define OCELOT_3_PCI_IO_1_SIZE 0x08000000
227#define OCELOT_3_PCI_MEM_1_START 0xd0000000
228#define OCELOT_3_PCI_MEM_1_SIZE 0x10000000
229
230static struct resource mv_pci_io_mem0_resource = {
231 .name = "MV64340 PCI0 IO MEM",
232 .start = OCELOT_3_PCI_IO_0_START,
233 .end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE - 1,
234 .flags = IORESOURCE_IO,
235};
236
237static struct resource mv_pci_io_mem1_resource = {
238 .name = "MV64340 PCI1 IO MEM",
239 .start = OCELOT_3_PCI_IO_1_START,
240 .end = OCELOT_3_PCI_IO_1_START + OCELOT_3_PCI_IO_1_SIZE - 1,
241 .flags = IORESOURCE_IO,
242};
243
244static struct resource mv_pci_mem0_resource = {
245 .name = "MV64340 PCI0 MEM",
246 .start = OCELOT_3_PCI_MEM_0_START,
247 .end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE - 1,
248 .flags = IORESOURCE_MEM,
249};
250
251static struct resource mv_pci_mem1_resource = {
252 .name = "MV64340 PCI1 MEM",
253 .start = OCELOT_3_PCI_MEM_1_START,
254 .end = OCELOT_3_PCI_MEM_1_START + OCELOT_3_PCI_MEM_1_SIZE - 1,
255 .flags = IORESOURCE_MEM,
256};
257
258static struct mv_pci_controller mv_bus0_controller = {
259 .pcic = {
260 .pci_ops = &mv_pci_ops,
261 .mem_resource = &mv_pci_mem0_resource,
262 .io_resource = &mv_pci_io_mem0_resource,
263 },
264 .config_addr = MV64340_PCI_0_CONFIG_ADDR,
265 .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
266};
267
268static struct mv_pci_controller mv_bus1_controller = {
269 .pcic = {
270 .pci_ops = &mv_pci_ops,
271 .mem_resource = &mv_pci_mem1_resource,
272 .io_resource = &mv_pci_io_mem1_resource,
273 },
274 .config_addr = MV64340_PCI_1_CONFIG_ADDR,
275 .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
276};
277
278static __init int __init ja_pci_init(void)
279{
280 uint32_t enable;
281 extern int pci_probe_only;
282
283 /* PMON will assign PCI resources */
284 pci_probe_only = 1;
285
286 enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
287 /*
288 * We require at least one enabled I/O or PCI memory window or we
289 * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
290 */
291 if (enable & (0x01 << 9) || enable & (0x01 << 10))
292 register_pci_controller(&mv_bus0_controller.pcic);
293
294 if (enable & (0x01 << 14) || enable & (0x01 << 15))
295 register_pci_controller(&mv_bus1_controller.pcic);
296
297 ioport_resource.end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE +
298 OCELOT_3_PCI_IO_1_SIZE - 1;
299
300 iomem_resource.end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE +
301 OCELOT_3_PCI_MEM_1_SIZE - 1;
302
303 set_io_port_base(OCELOT_3_PCI_IO_0_START); /* mips_io_port_base */
304
305 return 0;
306}
307
308arch_initcall(ja_pci_init);
309
310static int __init momenco_ocelot_3_setup(void)
311{
312 unsigned int tmpword;
313
314 board_time_init = momenco_time_init;
315
316 _machine_restart = momenco_ocelot_restart;
317 _machine_halt = momenco_ocelot_halt;
318 _machine_power_off = momenco_ocelot_power_off;
319
320 /* Wired TLB entries */
321 setup_wired_tlb_entries();
322
323 /* shut down ethernet ports, just to be sure our memory doesn't get
324 * corrupted by random ethernet traffic.
325 */
326 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
327 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
328 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
329 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
330 do {}
331 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
332 do {}
333 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
334 do {}
335 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
336 do {}
337 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
338 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
339 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
340 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
341 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
342
343 /* Turn off the Bit-Error LED */
344 OCELOT_FPGA_WRITE(0x80, CLR);
345
346 tmpword = OCELOT_FPGA_READ(BOARDREV);
347 if (tmpword < 26)
348 printk("Momenco Ocelot-3: Board Assembly Rev. %c\n",
349 'A'+tmpword);
350 else
351 printk("Momenco Ocelot-3: Board Assembly Revision #0x%x\n",
352 tmpword);
353
354 tmpword = OCELOT_FPGA_READ(FPGA_REV);
355 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
356 tmpword = OCELOT_FPGA_READ(RESET_STATUS);
357 printk("Reset reason: 0x%x\n", tmpword);
358 switch (tmpword) {
359 case 0x1:
360 printk(" - Power-up reset\n");
361 break;
362 case 0x2:
363 printk(" - Push-button reset\n");
364 break;
365 case 0x4:
366 printk(" - cPCI bus reset\n");
367 break;
368 case 0x8:
369 printk(" - Watchdog reset\n");
370 break;
371 case 0x10:
372 printk(" - Software reset\n");
373 break;
374 default:
375 printk(" - Unknown reset cause\n");
376 }
377 reset_reason = tmpword;
378 OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
379
380 tmpword = OCELOT_FPGA_READ(CPCI_ID);
381 printk("cPCI ID register: 0x%02x\n", tmpword);
382 printk(" - Slot number: %d\n", tmpword & 0x1f);
383 printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
384 printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
385
386 tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
387 printk("Board Status register: 0x%02x\n", tmpword);
388 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
389 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
390 printk(" - L3 cache size: %d MB\n", (1<<((tmpword&12) >> 2))&~1);
391
392 /* Support for 128 MB memory */
393 add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM);
394
395 return 0;
396}
397
398early_initcall(momenco_ocelot_3_setup);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 17:27:35 -0500