aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/momentum/jaguar_atx
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/momentum/jaguar_atx
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/mips/momentum/jaguar_atx')
-rw-r--r--arch/mips/momentum/jaguar_atx/Makefile12
-rw-r--r--arch/mips/momentum/jaguar_atx/dbg_io.c126
-rw-r--r--arch/mips/momentum/jaguar_atx/int-handler.S128
-rw-r--r--arch/mips/momentum/jaguar_atx/irq.c67
-rw-r--r--arch/mips/momentum/jaguar_atx/ja-console.c106
-rw-r--r--arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h52
-rw-r--r--arch/mips/momentum/jaguar_atx/prom.c266
-rw-r--r--arch/mips/momentum/jaguar_atx/reset.c57
-rw-r--r--arch/mips/momentum/jaguar_atx/setup.c474
9 files changed, 1288 insertions, 0 deletions
diff --git a/arch/mips/momentum/jaguar_atx/Makefile b/arch/mips/momentum/jaguar_atx/Makefile
new file mode 100644
index 000000000000..20bbd3ea44a8
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/Makefile
@@ -0,0 +1,12 @@
1#
2# Makefile for Momentum Computer's Jaguar-ATX board.
3#
4# Note! Dependencies are done automagically by 'make dep', which also
5# removes any old dependencies. DON'T put your own dependencies here
6# unless it's something special (ie not a .c file).
7#
8
9obj-y += int-handler.o irq.o prom.o reset.o setup.o
10
11obj-$(CONFIG_SERIAL_8250_CONSOLE) += ja-console.o
12obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
diff --git a/arch/mips/momentum/jaguar_atx/dbg_io.c b/arch/mips/momentum/jaguar_atx/dbg_io.c
new file mode 100644
index 000000000000..542eac82b63c
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/dbg_io.c
@@ -0,0 +1,126 @@
1#include <linux/config.h>
2
3#if defined(CONFIG_REMOTE_DEBUG)
4
5#include <asm/serial.h> /* For the serial port location and base baud */
6
7/* --- CONFIG --- */
8
9typedef unsigned char uint8;
10typedef unsigned int uint32;
11
12/* --- END OF CONFIG --- */
13
14#define UART16550_BAUD_2400 2400
15#define UART16550_BAUD_4800 4800
16#define UART16550_BAUD_9600 9600
17#define UART16550_BAUD_19200 19200
18#define UART16550_BAUD_38400 38400
19#define UART16550_BAUD_57600 57600
20#define UART16550_BAUD_115200 115200
21
22#define UART16550_PARITY_NONE 0
23#define UART16550_PARITY_ODD 0x08
24#define UART16550_PARITY_EVEN 0x18
25#define UART16550_PARITY_MARK 0x28
26#define UART16550_PARITY_SPACE 0x38
27
28#define UART16550_DATA_5BIT 0x0
29#define UART16550_DATA_6BIT 0x1
30#define UART16550_DATA_7BIT 0x2
31#define UART16550_DATA_8BIT 0x3
32
33#define UART16550_STOP_1BIT 0x0
34#define UART16550_STOP_2BIT 0x4
35
36/* ----------------------------------------------------- */
37
38/* === CONFIG === */
39
40/* [jsun] we use the second serial port for kdb */
41#define BASE OCELOT_SERIAL1_BASE
42#define MAX_BAUD OCELOT_BASE_BAUD
43
44/* === END OF CONFIG === */
45
46#define REG_OFFSET 4
47
48/* register offset */
49#define OFS_RCV_BUFFER 0
50#define OFS_TRANS_HOLD 0
51#define OFS_SEND_BUFFER 0
52#define OFS_INTR_ENABLE (1*REG_OFFSET)
53#define OFS_INTR_ID (2*REG_OFFSET)
54#define OFS_DATA_FORMAT (3*REG_OFFSET)
55#define OFS_LINE_CONTROL (3*REG_OFFSET)
56#define OFS_MODEM_CONTROL (4*REG_OFFSET)
57#define OFS_RS232_OUTPUT (4*REG_OFFSET)
58#define OFS_LINE_STATUS (5*REG_OFFSET)
59#define OFS_MODEM_STATUS (6*REG_OFFSET)
60#define OFS_RS232_INPUT (6*REG_OFFSET)
61#define OFS_SCRATCH_PAD (7*REG_OFFSET)
62
63#define OFS_DIVISOR_LSB (0*REG_OFFSET)
64#define OFS_DIVISOR_MSB (1*REG_OFFSET)
65
66
67/* memory-mapped read/write of the port */
68#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
69#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
70
71void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
72{
73 /* disable interrupts */
74 UART16550_WRITE(OFS_INTR_ENABLE, 0);
75
76 /* set up buad rate */
77 {
78 uint32 divisor;
79
80 /* set DIAB bit */
81 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
82
83 /* set divisor */
84 divisor = MAX_BAUD / baud;
85 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
86 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
87
88 /* clear DIAB bit */
89 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
90 }
91
92 /* set data format */
93 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
94}
95
96static int remoteDebugInitialized = 0;
97
98uint8 getDebugChar(void)
99{
100 if (!remoteDebugInitialized) {
101 remoteDebugInitialized = 1;
102 debugInit(UART16550_BAUD_38400,
103 UART16550_DATA_8BIT,
104 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
105 }
106
107 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
108 return UART16550_READ(OFS_RCV_BUFFER);
109}
110
111
112int putDebugChar(uint8 byte)
113{
114 if (!remoteDebugInitialized) {
115 remoteDebugInitialized = 1;
116 debugInit(UART16550_BAUD_38400,
117 UART16550_DATA_8BIT,
118 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
119 }
120
121 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
122 UART16550_WRITE(OFS_SEND_BUFFER, byte);
123 return 1;
124}
125
126#endif
diff --git a/arch/mips/momentum/jaguar_atx/int-handler.S b/arch/mips/momentum/jaguar_atx/int-handler.S
new file mode 100644
index 000000000000..43fd5a58077c
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/int-handler.S
@@ -0,0 +1,128 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on work:
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: jsun@mvista.com or jsun@junsun.net
8 *
9 * First-level interrupt dispatcher for Jaguar-ATX board.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <asm/asm.h>
17#include <asm/mipsregs.h>
18#include <asm/addrspace.h>
19#include <asm/regdef.h>
20#include <asm/stackframe.h>
21
22/*
23 * First level interrupt dispatcher for Ocelot-CS board
24 */
25 .align 5
26 NESTED(jaguar_handle_int, PT_SIZE, sp)
27 SAVE_ALL
28 CLI
29 .set at
30 mfc0 t0, CP0_CAUSE
31 mfc0 t2, CP0_STATUS
32
33 and t0, t2
34
35 andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */
36 bnez t1, ll_sw0_irq
37 andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */
38 bnez t1, ll_sw1_irq
39 andi t1, t0, STATUSF_IP2 /* int0 hardware line */
40 bnez t1, ll_pcixa_irq
41 andi t1, t0, STATUSF_IP3 /* int1 hardware line */
42 bnez t1, ll_pcixb_irq
43 andi t1, t0, STATUSF_IP4 /* int2 hardware line */
44 bnez t1, ll_pcia_irq
45 andi t1, t0, STATUSF_IP5 /* int3 hardware line */
46 bnez t1, ll_pcib_irq
47 andi t1, t0, STATUSF_IP6 /* int4 hardware line */
48 bnez t1, ll_uart_irq
49 andi t1, t0, STATUSF_IP7 /* cpu timer */
50 bnez t1, ll_cputimer_irq
51
52 nop
53 nop
54
55 /* now look at extended interrupts */
56 mfc0 t0, CP0_CAUSE
57 cfc0 t1, CP0_S1_INTCONTROL
58
59 /* shift the mask 8 bits left to line up the bits */
60 sll t2, t1, 8
61
62 and t0, t2
63 srl t0, t0, 16
64
65 andi t1, t0, STATUSF_IP8 /* int6 hardware line */
66 bnez t1, ll_mv64340_decode_irq
67
68 nop
69 nop
70
71 .set reorder
72
73 /* wrong alarm or masked ... */
74 j spurious_interrupt
75 nop
76 END(jaguar_handle_int)
77
78 .align 5
79ll_sw0_irq:
80 li a0, 0
81 move a1, sp
82 jal do_IRQ
83 j ret_from_irq
84ll_sw1_irq:
85 li a0, 1
86 move a1, sp
87 jal do_IRQ
88 j ret_from_irq
89ll_pcixa_irq:
90 li a0, 2
91 move a1, sp
92 jal do_IRQ
93 j ret_from_irq
94
95ll_pcixb_irq:
96 li a0, 3
97 move a1, sp
98 jal do_IRQ
99 j ret_from_irq
100
101ll_pcia_irq:
102 li a0, 4
103 move a1, sp
104 jal do_IRQ
105 j ret_from_irq
106
107ll_pcib_irq:
108 li a0, 5
109 move a1, sp
110 jal do_IRQ
111 j ret_from_irq
112
113ll_uart_irq:
114 li a0, 6
115 move a1, sp
116 jal do_IRQ
117 j ret_from_irq
118
119ll_cputimer_irq:
120 li a0, 7
121 move a1, sp
122 jal ll_timer_interrupt
123 j ret_from_irq
124
125ll_mv64340_decode_irq:
126 move a0, sp
127 jal ll_mv64340_irq
128 j ret_from_irq
diff --git a/arch/mips/momentum/jaguar_atx/irq.c b/arch/mips/momentum/jaguar_atx/irq.c
new file mode 100644
index 000000000000..15588f91ace2
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/irq.c
@@ -0,0 +1,67 @@
1/*
2 * Copyright (C) 2002 Momentum Computer, Inc.
3 * Author: Matthew Dharm, mdharm@momenco.com
4 *
5 * Based on work by:
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Author: RidgeRun, Inc.
8 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
9 *
10 * Copyright 2001 MontaVista Software Inc.
11 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
12 *
13 * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35#include <linux/init.h>
36#include <linux/interrupt.h>
37#include <linux/signal.h>
38#include <linux/types.h>
39#include <asm/irq_cpu.h>
40#include <asm/mipsregs.h>
41
42extern asmlinkage void jaguar_handle_int(void);
43
44static struct irqaction cascade_mv64340 = {
45 no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
46};
47
48void __init arch_init_irq(void)
49{
50 /*
51 * Clear all of the interrupts while we change the able around a bit.
52 * int-handler is not on bootstrap
53 */
54 clear_c0_status(ST0_IM);
55
56 /* Sets the first-level interrupt dispatcher. */
57 set_except_vector(0, jaguar_handle_int);
58 mips_cpu_irq_init(0);
59 rm7k_cpu_irq_init(8);
60
61 /* set up the cascading interrupts */
62 setup_irq(8, &cascade_mv64340);
63
64 mv64340_irq_init(16);
65
66 set_c0_status(ST0_IM);
67}
diff --git a/arch/mips/momentum/jaguar_atx/ja-console.c b/arch/mips/momentum/jaguar_atx/ja-console.c
new file mode 100644
index 000000000000..da6e1ed34db1
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/ja-console.c
@@ -0,0 +1,106 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2001, 2002, 2004 Ralf Baechle
7 */
8#include <linux/init.h>
9#include <linux/console.h>
10#include <linux/kdev_t.h>
11#include <linux/major.h>
12#include <linux/termios.h>
13#include <linux/sched.h>
14#include <linux/tty.h>
15
16#include <linux/serial.h>
17#include <linux/serial_core.h>
18#include <asm/serial.h>
19
20/* SUPERIO uart register map */
21struct ja_uartregs {
22 union {
23 volatile u8 pad0[3];
24 volatile u8 rbr; /* read only, DLAB == 0 */
25 volatile u8 pad1[3];
26 volatile u8 thr; /* write only, DLAB == 0 */
27 volatile u8 pad2[3];
28 volatile u8 dll; /* DLAB == 1 */
29 } u1;
30 union {
31 volatile u8 pad0[3];
32 volatile u8 ier; /* DLAB == 0 */
33 volatile u8 pad1[3];
34 volatile u8 dlm; /* DLAB == 1 */
35 } u2;
36 union {
37 volatile u8 pad0[3];
38 volatile u8 iir; /* read only */
39 volatile u8 pad1[3];
40 volatile u8 fcr; /* write only */
41 } u3;
42 volatile u8 pad0[3];
43 volatile u8 iu_lcr;
44 volatile u8 pad1[3];
45 volatile u8 iu_mcr;
46 volatile u8 pad2[3];
47 volatile u8 iu_lsr;
48 volatile u8 pad3[3];
49 volatile u8 iu_msr;
50 volatile u8 pad4[3];
51 volatile u8 iu_scr;
52} ja_uregs_t;
53
54#define iu_rbr u1.rbr
55#define iu_thr u1.thr
56#define iu_dll u1.dll
57#define iu_ier u2.ier
58#define iu_dlm u2.dlm
59#define iu_iir u3.iir
60#define iu_fcr u3.fcr
61
62extern unsigned long uart_base;
63
64static inline struct ja_uartregs *console_uart(void)
65{
66 return (struct ja_uartregs *) (uart_base + 0x23UL);
67}
68
69void prom_putchar(char c)
70{
71 struct ja_uartregs *uart = console_uart();
72
73 while ((uart->iu_lsr & 0x20) == 0);
74 uart->iu_thr = c;
75}
76
77char __init prom_getchar(void)
78{
79 return 0;
80}
81
82static void inline ja_console_probe(void)
83{
84 struct uart_port up;
85
86 /*
87 * Register to interrupt zero because we share the interrupt with
88 * the serial driver which we don't properly support yet.
89 */
90 memset(&up, 0, sizeof(up));
91 up.membase = (unsigned char *) uart_base + 0x23UL;
92 up.irq = JAGUAR_ATX_SERIAL1_IRQ;
93 up.uartclk = JAGUAR_ATX_UART_CLK;
94 up.regshift = 2;
95 up.iotype = UPIO_MEM;
96 up.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
97 up.line = 0;
98
99 if (early_serial_setup(&up))
100 printk(KERN_ERR "Early serial init of port 0 failed\n");
101}
102
103__init void ja_setup_console(void)
104{
105 ja_console_probe();
106}
diff --git a/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h b/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h
new file mode 100644
index 000000000000..6978654c712b
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h
@@ -0,0 +1,52 @@
1/*
2 * Jaguar-ATX Board Register Definitions
3 *
4 * (C) 2002 Momentum Computer Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#ifndef __JAGUAR_ATX_FPGA_H__
27#define __JAGUAR_ATX_FPGA_H__
28
29#define JAGUAR_ATX_REG_BOARDREV 0x0
30#define JAGUAR_ATX_REG_FPGA_REV 0x1
31#define JAGUAR_ATX_REG_FPGA_TYPE 0x2
32#define JAGUAR_ATX_REG_RESET_STATUS 0x3
33#define JAGUAR_ATX_REG_BOARD_STATUS 0x4
34#define JAGUAR_ATX_REG_RESERVED1 0x5
35#define JAGUAR_ATX_REG_SET 0x6
36#define JAGUAR_ATX_REG_CLR 0x7
37#define JAGUAR_ATX_REG_EEPROM_MODE 0x9
38#define JAGUAR_ATX_REG_RESERVED2 0xa
39#define JAGUAR_ATX_REG_RESERVED3 0xb
40#define JAGUAR_ATX_REG_RESERVED4 0xc
41#define JAGUAR_ATX_REG_PHY_INTSTAT 0xd
42#define JAGUAR_ATX_REG_RESERVED5 0xe
43#define JAGUAR_ATX_REG_RESERVED6 0xf
44
45#define JAGUAR_ATX_CS0_ADDR 0xfc000000L
46
47extern unsigned long ja_fpga_base;
48
49#define JAGUAR_FPGA_WRITE(x,y) writeb(x, ja_fpga_base + JAGUAR_ATX_REG_##y)
50#define JAGUAR_FPGA_READ(x) readb(ja_fpga_base + JAGUAR_ATX_REG_##x)
51
52#endif
diff --git a/arch/mips/momentum/jaguar_atx/prom.c b/arch/mips/momentum/jaguar_atx/prom.c
new file mode 100644
index 000000000000..fa5982ac0ac6
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/prom.c
@@ -0,0 +1,266 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Louis Hamilton, Red Hat, Inc.
6 * hamilton@redhat.com [MIPS64 modifications]
7 *
8 * Based on Ocelot Linux port, which is
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: jsun@mvista.com or jsun@junsun.net
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * Added changes for SMP - Manish Lachwani (lachwani@pmc-sierra.com)
18 */
19#include <linux/config.h>
20#include <linux/init.h>
21#include <linux/mm.h>
22#include <linux/sched.h>
23#include <linux/bootmem.h>
24
25#include <asm/addrspace.h>
26#include <asm/bootinfo.h>
27#include <asm/mv64340.h>
28#include <asm/pmon.h>
29
30#include "jaguar_atx_fpga.h"
31
32extern void ja_setup_console(void);
33
34struct callvectors *debug_vectors;
35
36extern unsigned long cpu_clock;
37
38const char *get_system_type(void)
39{
40 return "Momentum Jaguar-ATX";
41}
42
43#ifdef CONFIG_MV643XX_ETH
44extern unsigned char prom_mac_addr_base[6];
45
46static void burn_clocks(void)
47{
48 int i;
49
50 /* this loop should burn at least 1us -- this should be plenty */
51 for (i = 0; i < 0x10000; i++)
52 ;
53}
54
55static u8 exchange_bit(u8 val, u8 cs)
56{
57 /* place the data */
58 JAGUAR_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
59 burn_clocks();
60
61 /* turn the clock on */
62 JAGUAR_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
63 burn_clocks();
64
65 /* turn the clock off and read-strobe */
66 JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
67
68 /* return the data */
69 return ((JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
70}
71
72void get_mac(char dest[6])
73{
74 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
75 int i,j;
76
77 for (i = 0; i < 12; i++)
78 exchange_bit(read_opcode[i], 1);
79
80 for (j = 0; j < 6; j++) {
81 dest[j] = 0;
82 for (i = 0; i < 8; i++) {
83 dest[j] <<= 1;
84 dest[j] |= exchange_bit(0, 1);
85 }
86 }
87
88 /* turn off CS */
89 exchange_bit(0,0);
90}
91#endif
92
93#ifdef CONFIG_MIPS64
94
95unsigned long signext(unsigned long addr)
96{
97 addr &= 0xffffffff;
98 return (unsigned long)((int)addr);
99}
100
101void *get_arg(unsigned long args, int arc)
102{
103 unsigned long ul;
104 unsigned char *puc, uc;
105
106 args += (arc * 4);
107 ul = (unsigned long)signext(args);
108 puc = (unsigned char *)ul;
109 if (puc == 0)
110 return (void *)0;
111
112#ifdef CONFIG_CPU_LITTLE_ENDIAN
113 uc = *puc++;
114 l = (unsigned long)uc;
115 uc = *puc++;
116 ul |= (((unsigned long)uc) << 8);
117 uc = *puc++;
118 ul |= (((unsigned long)uc) << 16);
119 uc = *puc++;
120 ul |= (((unsigned long)uc) << 24);
121#else
122 uc = *puc++;
123 ul = ((unsigned long)uc) << 24;
124 uc = *puc++;
125 ul |= (((unsigned long)uc) << 16);
126 uc = *puc++;
127 ul |= (((unsigned long)uc) << 8);
128 uc = *puc++;
129 ul |= ((unsigned long)uc);
130#endif
131 ul = signext(ul);
132
133 return (void *)ul;
134}
135
136char *arg64(unsigned long addrin, int arg_index)
137{
138 unsigned long args;
139 char *p;
140
141 args = signext(addrin);
142 p = (char *)get_arg(args, arg_index);
143
144 return p;
145}
146#endif /* CONFIG_MIPS64 */
147
148/* PMON passes arguments in C main() style */
149void __init prom_init(void)
150{
151 int argc = fw_arg0;
152 char **arg = (char **) fw_arg1;
153 char **env = (char **) fw_arg2;
154 struct callvectors *cv = (struct callvectors *) fw_arg3;
155 int i;
156
157#ifdef CONFIG_SERIAL_8250_CONSOLE
158// ja_setup_console(); /* The very first thing. */
159#endif
160
161#ifdef CONFIG_MIPS64
162 char *ptr;
163
164 printk("Mips64 Jaguar-ATX\n");
165 /* save the PROM vectors for debugging use */
166 debug_vectors = (struct callvectors *)signext((unsigned long)cv);
167
168 /* arg[0] is "g", the rest is boot parameters */
169 arcs_cmdline[0] = '\0';
170
171 for (i = 1; i < argc; i++) {
172 ptr = (char *)arg64((unsigned long)arg, i);
173 if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
174 sizeof(arcs_cmdline))
175 break;
176 strcat(arcs_cmdline, ptr);
177 strcat(arcs_cmdline, " ");
178 }
179
180 i = 0;
181 while (1) {
182 ptr = (char *)arg64((unsigned long)env, i);
183 if (! ptr)
184 break;
185
186 if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
187 marvell_base = simple_strtol(ptr + strlen("gtbase="),
188 NULL, 16);
189
190 if ((marvell_base & 0xffffffff00000000) == 0)
191 marvell_base |= 0xffffffff00000000;
192
193 printk("marvell_base set to 0x%016lx\n", marvell_base);
194 }
195 if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
196 cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
197 NULL, 10);
198 printk("cpu_clock set to %d\n", cpu_clock);
199 }
200 i++;
201 }
202 printk("arcs_cmdline: %s\n", arcs_cmdline);
203
204#else /* CONFIG_MIPS64 */
205 /* save the PROM vectors for debugging use */
206 debug_vectors = cv;
207
208 /* arg[0] is "g", the rest is boot parameters */
209 arcs_cmdline[0] = '\0';
210 for (i = 1; i < argc; i++) {
211 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
212 >= sizeof(arcs_cmdline))
213 break;
214 strcat(arcs_cmdline, arg[i]);
215 strcat(arcs_cmdline, " ");
216 }
217
218 while (*env) {
219 if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
220 marvell_base = simple_strtol(*env + strlen("gtbase="),
221 NULL, 16);
222 }
223 if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
224 cpu_clock = simple_strtol(*env + strlen("cpuclock="),
225 NULL, 10);
226 }
227 env++;
228 }
229#endif /* CONFIG_MIPS64 */
230 mips_machgroup = MACH_GROUP_MOMENCO;
231 mips_machtype = MACH_MOMENCO_JAGUAR_ATX;
232
233#ifdef CONFIG_MV643XX_ETH
234 /* get the base MAC address for on-board ethernet ports */
235 get_mac(prom_mac_addr_base);
236#endif
237}
238
239void __init prom_free_prom_memory(void)
240{
241}
242
243void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
244{
245}
246
247int prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp)
248{
249 /* Clear the semaphore */
250 *(volatile uint32_t *)(0xbb000a68) = 0x80000000;
251
252 return 1;
253}
254
255void prom_init_secondary(void)
256{
257 clear_c0_config(CONF_CM_CMASK);
258 set_c0_config(0x2);
259
260 clear_c0_status(ST0_IM);
261 set_c0_status(0x1ffff);
262}
263
264void prom_smp_finish(void)
265{
266}
diff --git a/arch/mips/momentum/jaguar_atx/reset.c b/arch/mips/momentum/jaguar_atx/reset.c
new file mode 100644
index 000000000000..48039484cdf9
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/reset.c
@@ -0,0 +1,57 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 * Copyright (C) 2002 Momentum Computer Inc.
12 * Author: Matthew Dharm <mdharm@momenco.com>
13 *
14 * Louis Hamilton, Red Hat, Inc.
15 * hamilton@redhat.com [MIPS64 modifications]
16 */
17#include <linux/config.h>
18#include <linux/sched.h>
19#include <linux/mm.h>
20#include <asm/io.h>
21#include <asm/pgtable.h>
22#include <asm/processor.h>
23#include <asm/reboot.h>
24#include <asm/system.h>
25#include <linux/delay.h>
26
27void momenco_jaguar_restart(char *command)
28{
29 /* base address of timekeeper portion of part */
30#ifdef CONFIG_MIPS64
31 void *nvram = (void*) 0xfffffffffc807000;
32#else
33 void *nvram = (void*) 0xfc807000;
34#endif
35 /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
36 writeb(0x84, nvram + 0xff7);
37
38 /* wait for the watchdog to go off */
39 mdelay(100+(1000/16));
40
41 /* if the watchdog fails for some reason, let people know */
42 printk(KERN_NOTICE "Watchdog reset failed\n");
43}
44
45void momenco_jaguar_halt(void)
46{
47 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
48 while (1)
49 __asm__(".set\tmips3\n\t"
50 "wait\n\t"
51 ".set\tmips0");
52}
53
54void momenco_jaguar_power_off(void)
55{
56 momenco_jaguar_halt();
57}
diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c
new file mode 100644
index 000000000000..30462e715066
--- /dev/null
+++ b/arch/mips/momentum/jaguar_atx/setup.c
@@ -0,0 +1,474 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Jaguar-ATX board dependent boot routines
4 *
5 * Copyright (C) 1996, 1997, 2001, 2004 Ralf Baechle (ralf@linux-mips.org)
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
9 *
10 * Author: Matthew Dharm, Momentum Computer
11 * mdharm@momenco.com
12 *
13 * Louis Hamilton, Red Hat, Inc.
14 * hamilton@redhat.com [MIPS64 modifications]
15 *
16 * Author: RidgeRun, Inc.
17 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
18 *
19 * Copyright 2001 MontaVista Software Inc.
20 * Author: jsun@mvista.com or jsun@junsun.net
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License as published by the
24 * Free Software Foundation; either version 2 of the License, or (at your
25 * option) any later version.
26 *
27 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
30 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
33 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * You should have received a copy of the GNU General Public License along
39 * with this program; if not, write to the Free Software Foundation, Inc.,
40 * 675 Mass Ave, Cambridge, MA 02139, USA.
41 */
42#include <linux/config.h>
43#include <linux/bcd.h>
44#include <linux/init.h>
45#include <linux/kernel.h>
46#include <linux/types.h>
47#include <linux/mm.h>
48#include <linux/bootmem.h>
49#include <linux/module.h>
50#include <linux/pci.h>
51#include <linux/swap.h>
52#include <linux/ioport.h>
53#include <linux/sched.h>
54#include <linux/interrupt.h>
55#include <linux/timex.h>
56#include <linux/vmalloc.h>
57#include <asm/time.h>
58#include <asm/bootinfo.h>
59#include <asm/page.h>
60#include <asm/io.h>
61#include <asm/irq.h>
62#include <asm/processor.h>
63#include <asm/ptrace.h>
64#include <asm/reboot.h>
65#include <asm/tlbflush.h>
66#include <asm/mv64340.h>
67
68#include "jaguar_atx_fpga.h"
69
70extern unsigned long mv64340_sram_base;
71unsigned long cpu_clock;
72
73/* These functions are used for rebooting or halting the machine*/
74extern void momenco_jaguar_restart(char *command);
75extern void momenco_jaguar_halt(void);
76extern void momenco_jaguar_power_off(void);
77
78void momenco_time_init(void);
79
80static char reset_reason;
81
82static inline unsigned long ENTRYLO(unsigned long paddr)
83{
84 return ((paddr & PAGE_MASK) |
85 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
86 _CACHE_UNCACHED)) >> 6;
87}
88
89void __init bus_error_init(void) { /* nothing */ }
90
91/*
92 * Load a few TLB entries for the MV64340 and perhiperals. The MV64340 is going
93 * to be hit on every IRQ anyway - there's absolutely no point in letting it be
94 * a random TLB entry, as it'll just cause needless churning of the TLB. And we
95 * use the other half for the serial port, which is just a PITA otherwise :)
96 *
97 * Device Physical Virtual
98 * MV64340 Internal Regs 0xf4000000 0xf4000000
99 * Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
100 * NVRAM (CS1) 0xfc800000 0xfc800000
101 * UARTs (CS2) 0xfd000000 0xfd000000
102 * Internal SRAM 0xfe000000 0xfe000000
103 * M-Systems DOC (CS3) 0xff000000 0xff000000
104 */
105
106static __init void wire_stupidity_into_tlb(void)
107{
108#ifdef CONFIG_MIPS32
109 write_c0_wired(0);
110 local_flush_tlb_all();
111
112 /* marvell and extra space */
113 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
114 0xf4000000UL, PM_64K);
115 /* fpga, rtc, and uart */
116 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000),
117 0xfc000000UL, PM_16M);
118// /* m-sys and internal SRAM */
119// add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000),
120// 0xfe000000UL, PM_16M);
121
122 marvell_base = 0xf4000000;
123 //mv64340_sram_base = 0xfe000000; /* Currently unused */
124#endif
125}
126
127unsigned long marvell_base = 0xf4000000L;
128unsigned long ja_fpga_base = JAGUAR_ATX_CS0_ADDR;
129unsigned long uart_base = 0xfd000000L;
130static unsigned char *rtc_base = (unsigned char*) 0xfc800000L;
131
132EXPORT_SYMBOL(marvell_base);
133
134static __init int per_cpu_mappings(void)
135{
136 marvell_base = (unsigned long) ioremap(0xf4000000, 0x10000);
137 ja_fpga_base = (unsigned long) ioremap(JAGUAR_ATX_CS0_ADDR, 0x1000);
138 uart_base = (unsigned long) ioremap(0xfd000000UL, 0x1000);
139 rtc_base = ioremap(0xfc000000UL, 0x8000);
140 // ioremap(0xfe000000, 32 << 20);
141 write_c0_wired(0);
142 local_flush_tlb_all();
143 ja_setup_console();
144
145 return 0;
146}
147arch_initcall(per_cpu_mappings);
148
149unsigned long m48t37y_get_time(void)
150{
151 unsigned int year, month, day, hour, min, sec;
152
153 /* stop the update */
154 rtc_base[0x7ff8] = 0x40;
155
156 year = BCD2BIN(rtc_base[0x7fff]);
157 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
158
159 month = BCD2BIN(rtc_base[0x7ffe]);
160
161 day = BCD2BIN(rtc_base[0x7ffd]);
162
163 hour = BCD2BIN(rtc_base[0x7ffb]);
164 min = BCD2BIN(rtc_base[0x7ffa]);
165 sec = BCD2BIN(rtc_base[0x7ff9]);
166
167 /* start the update */
168 rtc_base[0x7ff8] = 0x00;
169
170 return mktime(year, month, day, hour, min, sec);
171}
172
173int m48t37y_set_time(unsigned long sec)
174{
175 struct rtc_time tm;
176
177 /* convert to a more useful format -- note months count from 0 */
178 to_tm(sec, &tm);
179 tm.tm_mon += 1;
180
181 /* enable writing */
182 rtc_base[0x7ff8] = 0x80;
183
184 /* year */
185 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
186 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
187
188 /* month */
189 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
190
191 /* day */
192 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
193
194 /* hour/min/sec */
195 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
196 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
197 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
198
199 /* day of week -- not really used, but let's keep it up-to-date */
200 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
201
202 /* disable writing */
203 rtc_base[0x7ff8] = 0x00;
204
205 return 0;
206}
207
208void momenco_timer_setup(struct irqaction *irq)
209{
210 setup_irq(8, irq);
211}
212
213/*
214 * Ugly but the least of all evils. TLB initialization did flush the TLB so
215 * We need to setup mappings again before we can touch the RTC.
216 */
217void momenco_time_init(void)
218{
219 wire_stupidity_into_tlb();
220
221 mips_hpt_frequency = cpu_clock / 2;
222 board_timer_setup = momenco_timer_setup;
223
224 rtc_get_time = m48t37y_get_time;
225 rtc_set_time = m48t37y_set_time;
226}
227
228static struct resource mv_pci_io_mem0_resource = {
229 .name = "MV64340 PCI0 IO MEM",
230 .flags = IORESOURCE_IO
231};
232
233static struct resource mv_pci_mem0_resource = {
234 .name = "MV64340 PCI0 MEM",
235 .flags = IORESOURCE_MEM
236};
237
238static struct mv_pci_controller mv_bus0_controller = {
239 .pcic = {
240 .pci_ops = &mv_pci_ops,
241 .mem_resource = &mv_pci_mem0_resource,
242 .io_resource = &mv_pci_io_mem0_resource,
243 },
244 .config_addr = MV64340_PCI_0_CONFIG_ADDR,
245 .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
246};
247
248static uint32_t mv_io_base, mv_io_size;
249
250static void ja_pci0_init(void)
251{
252 uint32_t mem0_base, mem0_size;
253 uint32_t io_base, io_size;
254
255 io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
256 io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
257 mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
258 mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
259
260 mv_pci_io_mem0_resource.start = 0;
261 mv_pci_io_mem0_resource.end = io_size - 1;
262 mv_pci_mem0_resource.start = mem0_base;
263 mv_pci_mem0_resource.end = mem0_base + mem0_size - 1;
264 mv_bus0_controller.pcic.mem_offset = mem0_base;
265 mv_bus0_controller.pcic.io_offset = 0;
266
267 ioport_resource.end = io_size - 1;
268
269 register_pci_controller(&mv_bus0_controller.pcic);
270
271 mv_io_base = io_base;
272 mv_io_size = io_size;
273}
274
275static struct resource mv_pci_io_mem1_resource = {
276 .name = "MV64340 PCI1 IO MEM",
277 .flags = IORESOURCE_IO
278};
279
280static struct resource mv_pci_mem1_resource = {
281 .name = "MV64340 PCI1 MEM",
282 .flags = IORESOURCE_MEM
283};
284
285static struct mv_pci_controller mv_bus1_controller = {
286 .pcic = {
287 .pci_ops = &mv_pci_ops,
288 .mem_resource = &mv_pci_mem1_resource,
289 .io_resource = &mv_pci_io_mem1_resource,
290 },
291 .config_addr = MV64340_PCI_1_CONFIG_ADDR,
292 .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
293};
294
295static __init void ja_pci1_init(void)
296{
297 uint32_t mem0_base, mem0_size;
298 uint32_t io_base, io_size;
299
300 io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
301 io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
302 mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
303 mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
304
305 /*
306 * Here we assume the I/O window of second bus to be contiguous with
307 * the first. A gap is no problem but would waste address space for
308 * remapping the port space.
309 */
310 mv_pci_io_mem1_resource.start = mv_io_size;
311 mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
312 mv_pci_mem1_resource.start = mem0_base;
313 mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
314 mv_bus1_controller.pcic.mem_offset = mem0_base;
315 mv_bus1_controller.pcic.io_offset = 0;
316
317 ioport_resource.end = io_base + io_size -mv_io_base - 1;
318
319 register_pci_controller(&mv_bus1_controller.pcic);
320
321 mv_io_size = io_base + io_size - mv_io_base;
322}
323
324static __init int __init ja_pci_init(void)
325{
326 unsigned long io_v_base;
327 uint32_t enable;
328
329 enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
330
331 /*
332 * We require at least one enabled I/O or PCI memory window or we
333 * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
334 */
335 if (enable & (0x01 << 9) || enable & (0x01 << 10))
336 ja_pci0_init();
337
338 if (enable & (0x01 << 14) || enable & (0x01 << 15))
339 ja_pci1_init();
340
341 if (mv_io_size) {
342 io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size);
343 if (!io_v_base)
344 panic("Could not ioremap I/O port range");
345
346 set_io_port_base(io_v_base);
347 }
348
349 return 0;
350}
351
352arch_initcall(ja_pci_init);
353
354static int __init momenco_jaguar_atx_setup(void)
355{
356 unsigned int tmpword;
357
358 board_time_init = momenco_time_init;
359
360 _machine_restart = momenco_jaguar_restart;
361 _machine_halt = momenco_jaguar_halt;
362 _machine_power_off = momenco_jaguar_power_off;
363
364 /*
365 * initrd_start = (ulong)jaguar_initrd_start;
366 * initrd_end = (ulong)jaguar_initrd_start + (ulong)jaguar_initrd_size;
367 * initrd_below_start_ok = 1;
368 */
369
370 wire_stupidity_into_tlb();
371
372 /*
373 * shut down ethernet ports, just to be sure our memory doesn't get
374 * corrupted by random ethernet traffic.
375 */
376 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
377 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
378 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
379 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
380 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
381 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
382 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
383 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
384 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
385 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
386 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
387 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
388 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
389 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
390 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
391 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
392 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2),
393 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
394
395 /* Turn off the Bit-Error LED */
396 JAGUAR_FPGA_WRITE(0x80, CLR);
397
398 tmpword = JAGUAR_FPGA_READ(BOARDREV);
399 if (tmpword < 26)
400 printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n",
401 'A'+tmpword);
402 else
403 printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n",
404 tmpword);
405
406 tmpword = JAGUAR_FPGA_READ(FPGA_REV);
407 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
408 tmpword = JAGUAR_FPGA_READ(RESET_STATUS);
409 printk("Reset reason: 0x%x\n", tmpword);
410 switch (tmpword) {
411 case 0x1:
412 printk(" - Power-up reset\n");
413 break;
414 case 0x2:
415 printk(" - Push-button reset\n");
416 break;
417 case 0x8:
418 printk(" - Watchdog reset\n");
419 break;
420 case 0x10:
421 printk(" - JTAG reset\n");
422 break;
423 default:
424 printk(" - Unknown reset cause\n");
425 }
426 reset_reason = tmpword;
427 JAGUAR_FPGA_WRITE(0xff, RESET_STATUS);
428
429 tmpword = JAGUAR_FPGA_READ(BOARD_STATUS);
430 printk("Board Status register: 0x%02x\n", tmpword);
431 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
432 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
433
434 /* 256MiB of RM9000x2 DDR */
435// add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
436
437 /* 128MiB of MV-64340 DDR */
438// add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
439
440 /* XXX Memory configuration should be picked up from PMON2k */
441#ifdef CONFIG_JAGUAR_DMALOW
442 printk("Jaguar ATX DMA-low mode set\n");
443 add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM);
444 add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM);
445#else
446 /* 128MiB of MV-64340 DDR RAM */
447 printk("Jaguar ATX DMA-low mode is not set\n");
448 add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
449#endif
450
451#ifdef GEMDEBUG_TRACEBUFFER
452 {
453 unsigned int tbControl;
454 tbControl =
455 0 << 26 | /* post trigger delay 0 */
456 0x2 << 16 | /* sequential trace mode */
457 // 0x0 << 16 | /* non-sequential trace mode */
458 // 0xf << 4 | /* watchpoints disabled */
459 2 << 2 | /* armed */
460 2 ; /* interrupt disabled */
461 printk ("setting tbControl = %08lx\n", tbControl);
462 write_32bit_cp0_set1_register($22, tbControl);
463 __asm__ __volatile__(".set noreorder\n\t" \
464 "nop; nop; nop; nop; nop; nop;\n\t" \
465 "nop; nop; nop; nop; nop; nop;\n\t" \
466 ".set reorder\n\t");
467
468 }
469#endif
470
471 return 0;
472}
473
474early_initcall(momenco_jaguar_atx_setup);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 04:36:02 -0500