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authorManuel Lauss <mano@roarinelk.homelinux.net>2009-03-25 12:49:30 -0400
committerRalf Baechle <ralf@linux-mips.org>2009-03-30 08:49:46 -0400
commit2f794d099da2f081de2fe19b289a3aa807f735fa (patch)
tree9d4065219b135c17c94a532fd8b4d51e49535f72 /arch/mips/mm
parent32647e0c1f63eead3e84d52b3edb8bc2f1fa2dd4 (diff)
MIPS: Alchemy: MIPS hazard workarounds are not required.
The Alchemy manuals state: "All pipeline hazards and dependencies are enforced by hardware interlocks so that any sequence of instructions is guaranteed to execute correctly. Therefore, it is not necessary to pad legacy MIPS hazards (such as load delay slots and coprocessor accesses) with NOPs." Run-tested on Au12x0, without any ill effects. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/tlbex.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 122c9c12e75a..0615b62efd6d 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -292,7 +292,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
292 case CPU_R4300: 292 case CPU_R4300:
293 case CPU_5KC: 293 case CPU_5KC:
294 case CPU_TX49XX: 294 case CPU_TX49XX:
295 case CPU_ALCHEMY:
296 case CPU_PR4450: 295 case CPU_PR4450:
297 uasm_i_nop(p); 296 uasm_i_nop(p);
298 tlbw(p); 297 tlbw(p);
@@ -315,6 +314,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
315 case CPU_R5500: 314 case CPU_R5500:
316 if (m4kc_tlbp_war()) 315 if (m4kc_tlbp_war())
317 uasm_i_nop(p); 316 uasm_i_nop(p);
317 case CPU_ALCHEMY:
318 tlbw(p); 318 tlbw(p);
319 break; 319 break;
320 320