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authorFlorian Fainelli <florian@openwrt.org>2012-01-31 12:18:45 -0500
committerJohn Crispin <blogic@openwrt.org>2012-08-22 17:46:38 -0400
commit62cedc4fde2d15b08e4502aa3fb2d9d798f3ccd8 (patch)
treefee5a50adcb7181d44bf4f3364d46883bc49dd35 /arch/mips/mm
parent91405eb69ee007ee854aa917e2a15e6ccede2cd1 (diff)
MIPS: introduce CPU_R4K_CACHE_TLB
R4K-style CPUs having common code to support their caches and tlb have this boolean defined by default. Allows us to remove some lines in arch/mips/mm/Makefile. Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/3328/ Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/Makefile17
1 files changed, 1 insertions, 16 deletions
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index fd6203f14f1f..90ceb963aaf1 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -11,27 +11,12 @@ obj-$(CONFIG_64BIT) += pgtable-64.o
11obj-$(CONFIG_HIGHMEM) += highmem.o 11obj-$(CONFIG_HIGHMEM) += highmem.o
12obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o 12obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
13 13
14obj-$(CONFIG_CPU_LOONGSON2) += c-r4k.o cex-gen.o tlb-r4k.o 14obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
15obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o tlb-r4k.o
16obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o tlb-r4k.o
17obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o tlb-r4k.o
18obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o tlb-r4k.o
19obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o 15obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o
20obj-$(CONFIG_CPU_R4300) += c-r4k.o cex-gen.o tlb-r4k.o
21obj-$(CONFIG_CPU_R4X00) += c-r4k.o cex-gen.o tlb-r4k.o
22obj-$(CONFIG_CPU_R5000) += c-r4k.o cex-gen.o tlb-r4k.o
23obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o tlb-r4k.o
24obj-$(CONFIG_CPU_R5500) += c-r4k.o cex-gen.o tlb-r4k.o
25obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o 16obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o
26obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o tlb-r4k.o
27obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o tlb-r4k.o
28obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o 17obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
29obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o 18obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o
30obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o
31obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o
32obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o 19obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
33obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o
34obj-$(CONFIG_CPU_XLP) += c-r4k.o tlb-r4k.o cex-gen.o
35 20
36obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o 21obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
37obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o 22obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o