Merge branch 'wip-mips-pm' of https://github.com/paulburton/linux into mips-for-linux-next

6 files changed, 100 insertions, 9 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 5c2128283ba6..587a14874f98 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -7,6 +7,7 @@
  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  */
+#include <linux/cpu_pm.h>
 #include <linux/hardirq.h>
 #include <linux/init.h>
 #include <linux/highmem.h>
@@ -1643,3 +1644,26 @@ void r4k_cache_init(void)
         coherency_setup();
         board_cache_error_setup = r4k_cache_error_setup;
 }
+
+static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
+                               void *v)
+{
+        switch (cmd) {
+        case CPU_PM_ENTER_FAILED:
+        case CPU_PM_EXIT:
+                coherency_setup();
+                break;
+        }
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block r4k_cache_pm_notifier_block = {
+        .notifier_call = r4k_cache_pm_notifier,
+};
+
+int __init r4k_cache_init_pm(void)
+{
+        return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
+}
+arch_initcall(r4k_cache_init_pm);
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 609a0cd749ff..6e4413330e36 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -79,7 +79,7 @@ void setup_zero_pages(void)
         zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK;
 }
 
-void *kmap_coherent(struct page *page, unsigned long addr)
+static void *__kmap_pgprot(struct page *page, unsigned long addr, pgprot_t prot)
 {
         enum fixed_addresses idx;
         unsigned long vaddr, flags, entrylo;
@@ -93,7 +93,7 @@ void *kmap_coherent(struct page *page, unsigned long addr)
         idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
         idx += in_interrupt() ? FIX_N_COLOURS : 0;
         vaddr = __fix_to_virt(FIX_CMAP_END - idx);
-        pte = mk_pte(page, PAGE_KERNEL);
+        pte = mk_pte(page, prot);
 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
         entrylo = pte.pte_high;
 #else
@@ -117,6 +117,16 @@ void *kmap_coherent(struct page *page, unsigned long addr)
         return (void*) vaddr;
 }
 
+void *kmap_coherent(struct page *page, unsigned long addr)
+{
+        return __kmap_pgprot(page, addr, PAGE_KERNEL);
+}
+
+void *kmap_noncoherent(struct page *page, unsigned long addr)
+{
+        return __kmap_pgprot(page, addr, PAGE_KERNEL_NC);
+}
+
 void kunmap_coherent(void)
 {
         unsigned int wired;
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 403fa804e4f4..3914e27456f2 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -8,6 +8,7 @@
  * Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
  */
+#include <linux/cpu_pm.h>
 #include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
@@ -399,7 +400,10 @@ static int __init set_ntlb(char *str)
 
 __setup("ntlb=", set_ntlb);
 
-void tlb_init(void)
+/*
+ * Configure TLB (for init or after a CPU has been powered off).
+ */
+static void r4k_tlb_configure(void)
 {
         /*
          * You should never change this register:
@@ -431,6 +435,11 @@ void tlb_init(void)
         local_flush_tlb_all();
 
         /* Did I tell you that ARC SUCKS?  */
+}
+
+void tlb_init(void)
+{
+        r4k_tlb_configure();
 
         if (ntlb) {
                 if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
@@ -444,3 +453,26 @@ void tlb_init(void)
 
         build_tlb_refill_handler();
 }
+
+static int r4k_tlb_pm_notifier(struct notifier_block *self, unsigned long cmd,
+                               void *v)
+{
+        switch (cmd) {
+        case CPU_PM_ENTER_FAILED:
+        case CPU_PM_EXIT:
+                r4k_tlb_configure();
+                break;
+        }
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block r4k_tlb_pm_notifier_block = {
+        .notifier_call = r4k_tlb_pm_notifier,
+};
+
+static int __init r4k_tlb_init_pm(void)
+{
+        return cpu_pm_register_notifier(&r4k_tlb_pm_notifier_block);
+}
+arch_initcall(r4k_tlb_init_pm);
diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c
index b8d580ca02e5..bcbcf4ae69b7 100644
--- a/arch/mips/mm/uasm-micromips.c
+++ b/arch/mips/mm/uasm-micromips.c
@@ -99,10 +99,12 @@ static struct insn insn_table_MM[] = {
         { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD },
         { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD },
         { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
+        { insn_sync, M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS },
         { insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 },
         { insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 },
         { insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 },
         { insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 },
+        { insn_wait, M(mm_pool32a_op, 0, 0, 0, mm_wait_op, mm_pool32axf_op), SCIMM },
         { insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD },
         { insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
         { insn_dins, 0, 0 },
diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c
index 3abd609518c9..4a2fc82fcd4f 100644
--- a/arch/mips/mm/uasm-mips.c
+++ b/arch/mips/mm/uasm-mips.c
@@ -82,6 +82,7 @@ static struct insn insn_table[] = {
         { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE },
         { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
         { insn_jal,  M(jal_op, 0, 0, 0, 0, 0),  JIMM },
+        { insn_jalr,  M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD },
         { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
         { insn_jr,  M(spec_op, 0, 0, 0, 0, jr_op),  RS },
         { insn_ld,  M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
@@ -106,13 +107,16 @@ static struct insn insn_table[] = {
         { insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },
         { insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },
         { insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_sync, M(spec_op, 0, 0, 0, 0, sync_op), RE },
         { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
         { insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },
         { insn_tlbr,  M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0 },
         { insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },
         { insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
+        { insn_wait, M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM },
         { insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
         { insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
+        { insn_yield, M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD },
         { insn_invalid, 0, 0 }
 };
 
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index b9d14b6c7f58..55a1fdfb76ef 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -49,12 +49,12 @@ enum opcode {
         insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
         insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
         insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
-        insn_ext, insn_ins, insn_j, insn_jal, insn_jr, insn_ld, insn_ldx,
-        insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0,
-        insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd,
-        insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
-        insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor,
-        insn_xori,
+        insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld,
+        insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0,
+        insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc,
+        insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
+        insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr,
+        insn_wait, insn_xor, insn_xori, insn_yield,
 };
 
 struct insn {
@@ -200,6 +200,13 @@ Ip_u1u2(op)						\
 }                                                       \
 UASM_EXPORT_SYMBOL(uasm_i##op);
 
+#define I_u2u1(op)                                      \
+Ip_u1u2(op)                                             \
+{                                                       \
+        build_insn(buf, insn##op, b, a);                \
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
+
 #define I_u1s2(op)                                      \
 Ip_u1s2(op)                                             \
 {                                                       \
@@ -250,6 +257,7 @@ I_u2u1msbdu3(_ext)
 I_u2u1msbu3(_ins)
 I_u1(_j)
 I_u1(_jal)
+I_u2u1(_jalr)
 I_u1(_jr)
 I_u2s3u1(_ld)
 I_u2s3u1(_ll)
@@ -270,12 +278,15 @@ I_u2u1u3(_srl)
 I_u2u1u3(_rotr)
 I_u3u1u2(_subu)
 I_u2s3u1(_sw)
+I_u1(_sync)
 I_0(_tlbp)
 I_0(_tlbr)
 I_0(_tlbwi)
 I_0(_tlbwr)
+I_u1(_wait);
 I_u3u1u2(_xor)
 I_u2u1u3(_xori)
+I_u2u1(_yield)
 I_u2u1msbu3(_dins);
 I_u2u1msb32u3(_dinsm);
 I_u1(_syscall);
@@ -469,6 +480,14 @@ void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
 }
 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));
 
+void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1,
+                          unsigned int r2, int lid)
+{
+        uasm_r_mips_pc16(r, *p, lid);
+        ISAFUNC(uasm_i_beq)(p, r1, r2, 0);
+}
+UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq));
+
 void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
                            int lid)
 {