diff options
author | Chris Dearman <chris@mips.com> | 2007-09-18 19:46:32 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2008-04-28 12:14:25 -0400 |
commit | 962f480e0f9024ecdcfe2ba1d216c038ee328ced (patch) | |
tree | 7bdc4f14bd9e894ed3178b3a9b6ec235710868a6 /arch/mips/mm | |
parent | 0bfa130e741f8f73a7bbf6a89aad4816e9094a71 (diff) |
[MIPS] All MIPS32 processors support64-bit physical addresses.
Still, only the 4K may actually implement it.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r-- | arch/mips/mm/init.c | 2 | ||||
-rw-r--r-- | arch/mips/mm/tlb-r4k.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index c7aed133d11d..235833af3a8b 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c | |||
@@ -142,7 +142,7 @@ void *kmap_coherent(struct page *page, unsigned long addr) | |||
142 | #endif | 142 | #endif |
143 | vaddr = __fix_to_virt(FIX_CMAP_END - idx); | 143 | vaddr = __fix_to_virt(FIX_CMAP_END - idx); |
144 | pte = mk_pte(page, PAGE_KERNEL); | 144 | pte = mk_pte(page, PAGE_KERNEL); |
145 | #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) | 145 | #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) |
146 | entrylo = pte.pte_high; | 146 | entrylo = pte.pte_high; |
147 | #else | 147 | #else |
148 | entrylo = pte_val(pte) >> 6; | 148 | entrylo = pte_val(pte) >> 6; |
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 63065d6e8063..5ce2fa745626 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c | |||
@@ -299,7 +299,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) | |||
299 | idx = read_c0_index(); | 299 | idx = read_c0_index(); |
300 | ptep = pte_offset_map(pmdp, address); | 300 | ptep = pte_offset_map(pmdp, address); |
301 | 301 | ||
302 | #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) | 302 | #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) |
303 | write_c0_entrylo0(ptep->pte_high); | 303 | write_c0_entrylo0(ptep->pte_high); |
304 | ptep++; | 304 | ptep++; |
305 | write_c0_entrylo1(ptep->pte_high); | 305 | write_c0_entrylo1(ptep->pte_high); |