diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2008-01-29 05:14:54 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2008-01-29 05:14:54 -0500 |
commit | 161548bf3529d53398adb3451cdc781cc324fc1d (patch) | |
tree | 47495cee5b14706a2228f1fc9cfa53813851d6aa /arch/mips/mm | |
parent | 6920df4025b426cb3c9756944a965fe9ccb30925 (diff) |
[MIPS] tlbex: Cleanup handling of R2 hazards in TLB handlers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r-- | arch/mips/mm/tlbex.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index a61246d3533d..511107f92d9c 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c | |||
@@ -860,6 +860,12 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, | |||
860 | case tlb_indexed: tlbw = i_tlbwi; break; | 860 | case tlb_indexed: tlbw = i_tlbwi; break; |
861 | } | 861 | } |
862 | 862 | ||
863 | if (cpu_has_mips_r2) { | ||
864 | i_ehb(p); | ||
865 | tlbw(p); | ||
866 | return; | ||
867 | } | ||
868 | |||
863 | switch (current_cpu_type()) { | 869 | switch (current_cpu_type()) { |
864 | case CPU_R4000PC: | 870 | case CPU_R4000PC: |
865 | case CPU_R4000SC: | 871 | case CPU_R4000SC: |
@@ -935,14 +941,6 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, | |||
935 | tlbw(p); | 941 | tlbw(p); |
936 | break; | 942 | break; |
937 | 943 | ||
938 | case CPU_4KEC: | ||
939 | case CPU_24K: | ||
940 | case CPU_34K: | ||
941 | case CPU_74K: | ||
942 | i_ehb(p); | ||
943 | tlbw(p); | ||
944 | break; | ||
945 | |||
946 | case CPU_RM9000: | 944 | case CPU_RM9000: |
947 | /* | 945 | /* |
948 | * When the JTLB is updated by tlbwi or tlbwr, a subsequent | 946 | * When the JTLB is updated by tlbwi or tlbwr, a subsequent |