diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2011-05-14 06:06:36 -0400 |
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committer | Thomas Gleixner <tglx@linutronix.de> | 2011-05-14 06:06:36 -0400 |
commit | a18f22a968de17b29f2310cdb7ba69163e65ec15 (patch) | |
tree | a7d56d88fad5e444d7661484109758a2f436129e /arch/mips/mm | |
parent | a1c57e0fec53defe745e64417eacdbd3618c3e66 (diff) | |
parent | 798778b8653f64b7b2162ac70eca10367cff6ce8 (diff) |
Merge branch 'consolidate-clksrc-i8253' of master.kernel.org:~rmk/linux-2.6-arm into timers/clocksource
Conflicts:
arch/ia64/kernel/cyclone.c
arch/mips/kernel/i8253.c
arch/x86/kernel/i8253.c
Reason: Resolve conflicts so further cleanups do not conflict further
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r-- | arch/mips/mm/cex-sb1.S | 2 | ||||
-rw-r--r-- | arch/mips/mm/init.c | 2 | ||||
-rw-r--r-- | arch/mips/mm/tlbex.c | 4 |
3 files changed, 5 insertions, 3 deletions
diff --git a/arch/mips/mm/cex-sb1.S b/arch/mips/mm/cex-sb1.S index 2d08268bb705..89c412bc4b64 100644 --- a/arch/mips/mm/cex-sb1.S +++ b/arch/mips/mm/cex-sb1.S | |||
@@ -79,7 +79,7 @@ LEAF(except_vec2_sb1) | |||
79 | recovered_dcache: | 79 | recovered_dcache: |
80 | /* | 80 | /* |
81 | * Unlock CacheErr-D (which in turn unlocks CacheErr-DPA). | 81 | * Unlock CacheErr-D (which in turn unlocks CacheErr-DPA). |
82 | * Ought to log the occurence of this recovered dcache error. | 82 | * Ought to log the occurrence of this recovered dcache error. |
83 | */ | 83 | */ |
84 | b recovered | 84 | b recovered |
85 | mtc0 $0,C0_CERR_D | 85 | mtc0 $0,C0_CERR_D |
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 2efcbd24c82f..279599e9a779 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c | |||
@@ -324,7 +324,7 @@ int page_is_ram(unsigned long pagenr) | |||
324 | void __init paging_init(void) | 324 | void __init paging_init(void) |
325 | { | 325 | { |
326 | unsigned long max_zone_pfns[MAX_NR_ZONES]; | 326 | unsigned long max_zone_pfns[MAX_NR_ZONES]; |
327 | unsigned long lastpfn; | 327 | unsigned long lastpfn __maybe_unused; |
328 | 328 | ||
329 | pagetable_init(); | 329 | pagetable_init(); |
330 | 330 | ||
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 083d3412d0bc..5ef294fbb6e7 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c | |||
@@ -109,6 +109,8 @@ static bool scratchpad_available(void) | |||
109 | static int scratchpad_offset(int i) | 109 | static int scratchpad_offset(int i) |
110 | { | 110 | { |
111 | BUG(); | 111 | BUG(); |
112 | /* Really unreachable, but evidently some GCC want this. */ | ||
113 | return 0; | ||
112 | } | 114 | } |
113 | #endif | 115 | #endif |
114 | /* | 116 | /* |
@@ -350,7 +352,7 @@ static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p) | |||
350 | 352 | ||
351 | /* | 353 | /* |
352 | * Write random or indexed TLB entry, and care about the hazards from | 354 | * Write random or indexed TLB entry, and care about the hazards from |
353 | * the preceeding mtc0 and for the following eret. | 355 | * the preceding mtc0 and for the following eret. |
354 | */ | 356 | */ |
355 | enum tlb_write_entry { tlb_random, tlb_indexed }; | 357 | enum tlb_write_entry { tlb_random, tlb_indexed }; |
356 | 358 | ||