Merge branch 'master' of /home/davem/src/GIT/linux-2.6/

3 files changed, 6 insertions, 3 deletions

diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 98ad0a82c29e..694d51f523d1 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -13,6 +13,7 @@
 #include <linux/linkage.h>
 #include <linux/module.h>
 #include <linux/sched.h>
+#include <linux/syscalls.h>
 #include <linux/mm.h>
 
 #include <asm/cacheflush.h>
@@ -58,8 +59,8 @@ EXPORT_SYMBOL(_dma_cache_wback_inv);
  * We could optimize the case where the cache argument is not BCACHE but
  * that seems very atypical use ...
  */
-asmlinkage int sys_cacheflush(unsigned long addr,
-        unsigned long bytes, unsigned int cache)
+SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, bytes,
+        unsigned int, cache)
 {
         if (bytes == 0)
                 return 0;
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 1417c6494858..48060c635acd 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -172,8 +172,9 @@ static void __cpuinit set_prefetch_parameters(void)
                  */
                 cache_line_size = cpu_dcache_line_size();
                 switch (current_cpu_type()) {
+                case CPU_R5500:
                 case CPU_TX49XX:
-                        /* TX49 supports only Pref_Load */
+                        /* These processors only support the Pref_Load. */
                         pref_bias_copy_load = 256;
                         break;
 
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 42942038d0fd..f335cf6cdd78 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -318,6 +318,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
         case CPU_BCM4710:
         case CPU_LOONGSON2:
         case CPU_CAVIUM_OCTEON:
+        case CPU_R5500:
                 if (m4kc_tlbp_war())
                         uasm_i_nop(p);
                 tlbw(p);