aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/mm
diff options
context:
space:
mode:
authorMaciej W. Rozycki <macro@linux-mips.org>2005-06-20 09:09:49 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:31:28 -0400
commitc6ad7b7d3cd7883810c05fad9d30303cf9368f63 (patch)
treeb8df8802eb177cac2e4588ea98b86077b076d9b5 /arch/mips/mm
parent8a185d14b665d454bde84c6ae067beade452e7f8 (diff)
Use macros for the RM7k cp0.config bits instead of magic numbers.
Minor clean-ups. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/sc-rm7k.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index 1df5aab82c13..9e8ff8badb19 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -103,7 +103,7 @@ static __init void __rm7k_sc_enable(void)
103{ 103{
104 int i; 104 int i;
105 105
106 set_c0_config(R7K_CONF_SE); 106 set_c0_config(RM7K_CONF_SE);
107 107
108 write_c0_taglo(0); 108 write_c0_taglo(0);
109 write_c0_taghi(0); 109 write_c0_taghi(0);
@@ -122,16 +122,16 @@ static __init void __rm7k_sc_enable(void)
122 122
123static __init void rm7k_sc_enable(void) 123static __init void rm7k_sc_enable(void)
124{ 124{
125 if (read_c0_config() & R7K_CONF_SE) 125 if (read_c0_config() & RM7K_CONF_SE)
126 return; 126 return;
127 127
128 printk(KERN_INFO "Enabling secondary cache..."); 128 printk(KERN_INFO "Enabling secondary cache...\n");
129 run_uncached(__rm7k_sc_enable); 129 run_uncached(__rm7k_sc_enable);
130} 130}
131 131
132static void rm7k_sc_disable(void) 132static void rm7k_sc_disable(void)
133{ 133{
134 clear_c0_config(R7K_CONF_SE); 134 clear_c0_config(RM7K_CONF_SE);
135} 135}
136 136
137struct bcache_ops rm7k_sc_ops = { 137struct bcache_ops rm7k_sc_ops = {
@@ -145,19 +145,19 @@ void __init rm7k_sc_init(void)
145{ 145{
146 unsigned int config = read_c0_config(); 146 unsigned int config = read_c0_config();
147 147
148 if ((config >> 31) & 1) /* Bit 31 set -> no S-Cache */ 148 if ((config & RM7K_CONF_SC))
149 return; 149 return;
150 150
151 printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n", 151 printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n",
152 (scache_size >> 10), sc_lsize); 152 (scache_size >> 10), sc_lsize);
153 153
154 if (!(config & R7K_CONF_SE)) 154 if (!(config & RM7K_CONF_SE))
155 rm7k_sc_enable(); 155 rm7k_sc_enable();
156 156
157 /* 157 /*
158 * While we're at it let's deal with the tertiary cache. 158 * While we're at it let's deal with the tertiary cache.
159 */ 159 */
160 if (!((config >> 17) & 1)) { 160 if (!(config & RM7K_CONF_TC)) {
161 161
162 /* 162 /*
163 * We can't enable the L3 cache yet. There may be board-specific 163 * We can't enable the L3 cache yet. There may be board-specific
@@ -170,9 +170,9 @@ void __init rm7k_sc_init(void)
170 * to probe it. 170 * to probe it.
171 */ 171 */
172 printk(KERN_INFO "Tertiary cache present, %s enabled\n", 172 printk(KERN_INFO "Tertiary cache present, %s enabled\n",
173 config&(1<<12) ? "already" : "not (yet)"); 173 (config & RM7K_CONF_TE) ? "already" : "not (yet)");
174 174
175 if ((config >> 12) & 1) 175 if ((config & RM7K_CONF_TE))
176 rm7k_tcache_enabled = 1; 176 rm7k_tcache_enabled = 1;
177 } 177 }
178 178