Better interface to run uncached cache setup code.

Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2 files changed, 10 insertions, 25 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 48d731c2f08a..b90147399ea4 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -26,6 +26,7 @@
 #include <asm/system.h>
 #include <asm/mmu_context.h>
 #include <asm/war.h>
+#include <asm/cacheflush.h> /* for run_uncached() */
 
 static unsigned long icache_size, dcache_size, scache_size;
 
@@ -1119,7 +1120,6 @@ static int __init probe_scache(void)
         return 1;
 }
 
-typedef int (*probe_func_t)(unsigned long);
 extern int r5k_sc_init(void);
 extern int rm7k_sc_init(void);
 
@@ -1127,7 +1127,6 @@ static void __init setup_scache(void)
 {
         struct cpuinfo_mips *c = &current_cpu_data;
         unsigned int config = read_c0_config();
-        probe_func_t probe_scache_kseg1;
         int sc_present = 0;
 
         /*
@@ -1140,8 +1139,7 @@ static void __init setup_scache(void)
         case CPU_R4000MC:
         case CPU_R4400SC:
         case CPU_R4400MC:
-                probe_scache_kseg1 = (probe_func_t) (CKSEG1ADDR(&probe_scache));
-                sc_present = probe_scache_kseg1(config);
+                sc_present = run_uncached(probe_scache);
                 if (sc_present)
                         c->options |= MIPS_CPU_CACHE_CDEX_S;
                 break;
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index 4e92f931aaba..1df5aab82c13 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -15,6 +15,7 @@
 #include <asm/cacheops.h>
 #include <asm/mipsregs.h>
 #include <asm/processor.h>
+#include <asm/cacheflush.h> /* for run_uncached() */
 
 /* Primary cache parameters. */
 #define sc_lsize        32
@@ -96,25 +97,13 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size)
 }
 
 /*
- * This function is executed in the uncached segment CKSEG1.
- * It must not touch the stack, because the stack pointer still points
- * into CKSEG0.
- *
- * Three options:
- *      - Write it in assembly and guarantee that we don't use the stack.
- *      - Disable caching for CKSEG0 before calling it.
- *      - Pray that GCC doesn't randomly start using the stack.
- *
- * This being Linux, we obviously take the least sane of those options -
- * following DaveM's lead in c-r4k.c
- *
- * It seems we get our kicks from relying on unguaranteed behaviour in GCC
+ * This function is executed in uncached address space.
  */
 static __init void __rm7k_sc_enable(void)
 {
         int i;
 
-        set_c0_config(1 << 3);                          /* CONF_SE */
+        set_c0_config(R7K_CONF_SE);
 
         write_c0_taglo(0);
         write_c0_taghi(0);
@@ -127,24 +116,22 @@ static __init void __rm7k_sc_enable(void)
                       ".set mips0\n\t"
                       ".set reorder"
                       :
-                      : "r" (KSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
+                      : "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
         }
 }
 
 static __init void rm7k_sc_enable(void)
 {
-        void (*func)(void) = (void *) KSEG1ADDR(&__rm7k_sc_enable);
-
-        if (read_c0_config() & 0x08)                    /* CONF_SE */
+        if (read_c0_config() & R7K_CONF_SE)
                 return;
 
         printk(KERN_INFO "Enabling secondary cache...");
-        func();
+        run_uncached(__rm7k_sc_enable);
 }
 
 static void rm7k_sc_disable(void)
 {
-        clear_c0_config(1<<3);                          /* CONF_SE */
+        clear_c0_config(R7K_CONF_SE);
 }
 
 struct bcache_ops rm7k_sc_ops = {
@@ -164,7 +151,7 @@ void __init rm7k_sc_init(void)
         printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n",
                (scache_size >> 10), sc_lsize);
 
-        if (!((config >> 3) & 1))       /* CONF_SE */
+        if (!(config & R7K_CONF_SE))
                 rm7k_sc_enable();
 
         /*