MIPS: PMC-Sierra Yosemite: Remove support.

Nobody seems to be interested anymore and upstream also never had an
ethernet driver.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 0 insertions, 31 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 2b6146241bde..d2b5b0c7afa0 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -936,7 +936,6 @@ static void __cpuinit probe_pcache(void)
         case CPU_RM7000:
                 rm7k_erratum31();
 
-        case CPU_RM9000:
                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
                 c->icache.ways = 4;
@@ -947,9 +946,7 @@ static void __cpuinit probe_pcache(void)
                 c->dcache.ways = 4;
                 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
 
-#if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
                 c->options |= MIPS_CPU_CACHE_CDEX_P;
-#endif
                 c->options |= MIPS_CPU_PREFETCH;
                 break;
 
@@ -1234,7 +1231,6 @@ static void __cpuinit setup_scache(void)
                 return;
 
         case CPU_RM7000:
-        case CPU_RM9000:
 #ifdef CONFIG_RM7000_CPU_SCACHE
                 rm7k_sc_init();
 #endif
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 98f530e18216..8e666c55f4d4 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -140,15 +140,6 @@ static void __cpuinit set_prefetch_parameters(void)
                         pref_bias_copy_load = 256;
                         break;
 
-                case CPU_RM9000:
-                        /*
-                         * As a workaround for erratum G105 which make the
-                         * PrepareForStore hint unusable we fall back to
-                         * StoreRetained on the RM9000.  Once it is known which
-                         * versions of the RM9000 we'll be able to condition-
-                         * alize this.
-                         */
-
                 case CPU_R10000:
                 case CPU_R12000:
                 case CPU_R14000:
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 6af62a2fec21..69a357254e46 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -603,24 +603,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
                 tlbw(p);
                 break;
 
-        case CPU_RM9000:
-                /*
-                 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
-                 * use of the JTLB for instructions should not occur for 4
-                 * cpu cycles and use for data translations should not occur
-                 * for 3 cpu cycles.
-                 */
-                uasm_i_ssnop(p);
-                uasm_i_ssnop(p);
-                uasm_i_ssnop(p);
-                uasm_i_ssnop(p);
-                tlbw(p);
-                uasm_i_ssnop(p);
-                uasm_i_ssnop(p);
-                uasm_i_ssnop(p);
-                uasm_i_ssnop(p);
-                break;
-
         case CPU_VR4111:
         case CPU_VR4121:
         case CPU_VR4122: