MIPS: Alchemy: unify CPU model constants.

This patch removes the various CPU_AU1??? model constants in favor of
a single CPU_ALCHEMY one.

All currently existing Alchemy models are identical in terms of cpu
core and cache size/organization.  The parts of the mips kernel which
need to know the exact CPU revision extract it from the c0_prid register
already; and finally nothing else in-tree depends on those any more.

Should a new variant with slightly different "company options" and/or
"processor revision" bits in c0_prid appear, it will be supported
immediately (minus an exact model string in cpuinfo).

Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2 files changed, 6 insertions, 19 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 871e828bc62a..58d9075e86fe 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1026,13 +1026,7 @@ static void __cpuinit probe_pcache(void)
                 c->icache.flags |= MIPS_CACHE_VTAG;
                 break;
 
-        case CPU_AU1000:
-        case CPU_AU1500:
-        case CPU_AU1100:
-        case CPU_AU1550:
-        case CPU_AU1200:
-        case CPU_AU1210:
-        case CPU_AU1250:
+        case CPU_ALCHEMY:
                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
                 break;
         }
@@ -1244,7 +1238,7 @@ void au1x00_fixup_config_od(void)
         /*
          * Au1100 errata actually keeps silence about this bit, so we set it
          * just in case for those revisions that require it to be set according
-         * to arch/mips/au1000/common/cputable.c
+         * to the (now gone) cpu table.
          */
         case 0x02030200: /* Au1100 AB */
         case 0x02030201: /* Au1100 BA */
@@ -1314,11 +1308,10 @@ static void __cpuinit coherency_setup(void)
                 break;
         /*
          * We need to catch the early Alchemy SOCs with
-         * the write-only co_config.od bit and set it back to one...
+         * the write-only co_config.od bit and set it back to one on:
+         * Au1000 rev DA, HA, HB;  Au1100 AB, BA, BC, Au1500 AB
          */
-        case CPU_AU1000: /* rev. DA, HA, HB */
-        case CPU_AU1100: /* rev. AB, BA, BC ?? */
-        case CPU_AU1500: /* rev. AB */
+        case CPU_ALCHEMY:
                 au1x00_fixup_config_od();
                 break;
 
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index f335cf6cdd78..122c9c12e75a 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -292,13 +292,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
         case CPU_R4300:
         case CPU_5KC:
         case CPU_TX49XX:
-        case CPU_AU1000:
-        case CPU_AU1100:
-        case CPU_AU1500:
-        case CPU_AU1550:
-        case CPU_AU1200:
-        case CPU_AU1210:
-        case CPU_AU1250:
+        case CPU_ALCHEMY:
         case CPU_PR4450:
                 uasm_i_nop(p);
                 tlbw(p);