diff options
author | David Daney <ddaney@caviumnetworks.com> | 2010-02-10 18:12:46 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2010-02-27 06:53:25 -0500 |
commit | 32546f38fab839eee6f62b3f06c2774eade4188a (patch) | |
tree | 582cb9fb18c8e741d24a4a27d9c2dee46bfd977f /arch/mips/mm | |
parent | 9fe2e9d6f5390d7151a0b9d8c100f0da26eaa2b7 (diff) |
MIPS: Add TLBR and ROTR to uasm.
The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and
ROTR support in uasm. We also add a UASM_i_ROTR macro.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/953/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r-- | arch/mips/mm/uasm.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index e3ca0f7ed01a..1581e9852461 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c | |||
@@ -62,8 +62,9 @@ enum opcode { | |||
62 | insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal, | 62 | insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal, |
63 | insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, | 63 | insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, |
64 | insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, | 64 | insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, |
65 | insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, | 65 | insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, |
66 | insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins | 66 | insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, |
67 | insn_dins | ||
67 | }; | 68 | }; |
68 | 69 | ||
69 | struct insn { | 70 | struct insn { |
@@ -125,9 +126,11 @@ static struct insn insn_table[] __cpuinitdata = { | |||
125 | { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, | 126 | { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, |
126 | { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, | 127 | { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, |
127 | { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, | 128 | { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, |
129 | { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE }, | ||
128 | { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, | 130 | { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, |
129 | { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, | 131 | { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
130 | { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, | 132 | { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, |
133 | { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, | ||
131 | { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, | 134 | { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, |
132 | { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, | 135 | { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, |
133 | { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, | 136 | { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, |
@@ -378,9 +381,11 @@ I_u2s3u1(_sd) | |||
378 | I_u2u1u3(_sll) | 381 | I_u2u1u3(_sll) |
379 | I_u2u1u3(_sra) | 382 | I_u2u1u3(_sra) |
380 | I_u2u1u3(_srl) | 383 | I_u2u1u3(_srl) |
384 | I_u2u1u3(_rotr) | ||
381 | I_u3u1u2(_subu) | 385 | I_u3u1u2(_subu) |
382 | I_u2s3u1(_sw) | 386 | I_u2s3u1(_sw) |
383 | I_0(_tlbp) | 387 | I_0(_tlbp) |
388 | I_0(_tlbr) | ||
384 | I_0(_tlbwi) | 389 | I_0(_tlbwi) |
385 | I_0(_tlbwr) | 390 | I_0(_tlbwr) |
386 | I_u3u1u2(_xor) | 391 | I_u3u1u2(_xor) |