More AP / SP bits for the 34K, the Malta bits and things. Still wants

a little polishing.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2 files changed, 3 insertions, 5 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index d3e352fb3243..6a1267ad071f 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1228,8 +1228,7 @@ void __init ld_mmu_r4xx0(void)
         struct cpuinfo_mips *c = &current_cpu_data;
 
         /* Default cache error handler for R4000 and R5000 family */
-        memcpy((void *)(CAC_BASE   + 0x100), &except_vec2_generic, 0x80);
-        memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80);
+        set_uncached_handler (0x100, &except_vec2_generic, 0x80);
 
         probe_pcache();
         setup_scache();
diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c
index e65b1bb576fd..d183dbced687 100644
--- a/arch/mips/mm/c-sb1.c
+++ b/arch/mips/mm/c-sb1.c
@@ -502,9 +502,8 @@ void ld_mmu_sb1(void)
         extern char handle_vec2_sb1;
 
         /* Special cache error handler for SB1 */
-        memcpy((void *)(CAC_BASE   + 0x100), &except_vec2_sb1, 0x80);
-        memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_sb1, 0x80);
-        memcpy((void *)CKSEG1ADDR(&handle_vec2_sb1), &handle_vec2_sb1, 0x80);
+        set_uncached_handler (0x100, &except_vec2_sb1, 0x80);
+        memcpy((void *)KSEG1ADDR(&handle_vec2_sb1), &handle_vec2_sb1, 0x80);
 
         probe_cache_sizes();