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authorRalf Baechle <ralf@linux-mips.org>2008-04-28 12:14:26 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-04-28 12:14:26 -0400
commit39b8d5254246ac56342b72f812255c8f7a74dca9 (patch)
treea9ec6bfb5d09a8367c34cc2067328d1b49bb46c1 /arch/mips/mm
parent308402445e005a039a72b315cd9b5ceeaea0063c (diff)
[MIPS] Add support for MIPS CMP platform.
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/c-r4k.c43
-rw-r--r--arch/mips/mm/init.c2
2 files changed, 38 insertions, 7 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 3d3e53651341..643c8bcffff3 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -54,6 +54,12 @@ static inline void r4k_on_each_cpu(void (*func) (void *info), void *info,
54 preempt_enable(); 54 preempt_enable();
55} 55}
56 56
57#if defined(CONFIG_MIPS_CMP)
58#define cpu_has_safe_index_cacheops 0
59#else
60#define cpu_has_safe_index_cacheops 1
61#endif
62
57/* 63/*
58 * Must die. 64 * Must die.
59 */ 65 */
@@ -482,6 +488,8 @@ static inline void local_r4k_flush_cache_page(void *args)
482 488
483 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 489 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
484 r4k_blast_dcache_page(addr); 490 r4k_blast_dcache_page(addr);
491 if (exec && !cpu_icache_snoops_remote_store)
492 r4k_blast_scache_page(addr);
485 } 493 }
486 if (exec) { 494 if (exec) {
487 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { 495 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
@@ -584,7 +592,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
584 * subset property so we have to flush the primary caches 592 * subset property so we have to flush the primary caches
585 * explicitly 593 * explicitly
586 */ 594 */
587 if (size >= dcache_size) { 595 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
588 r4k_blast_dcache(); 596 r4k_blast_dcache();
589 } else { 597 } else {
590 R4600_HIT_CACHEOP_WAR_IMPL; 598 R4600_HIT_CACHEOP_WAR_IMPL;
@@ -607,7 +615,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
607 return; 615 return;
608 } 616 }
609 617
610 if (size >= dcache_size) { 618 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
611 r4k_blast_dcache(); 619 r4k_blast_dcache();
612 } else { 620 } else {
613 R4600_HIT_CACHEOP_WAR_IMPL; 621 R4600_HIT_CACHEOP_WAR_IMPL;
@@ -969,6 +977,7 @@ static void __cpuinit probe_pcache(void)
969 case CPU_24K: 977 case CPU_24K:
970 case CPU_34K: 978 case CPU_34K:
971 case CPU_74K: 979 case CPU_74K:
980 case CPU_1004K:
972 if ((read_c0_config7() & (1 << 16))) { 981 if ((read_c0_config7() & (1 << 16))) {
973 /* effectively physically indexed dcache, 982 /* effectively physically indexed dcache,
974 thus no virtual aliases. */ 983 thus no virtual aliases. */
@@ -1265,6 +1274,20 @@ static void __cpuinit coherency_setup(void)
1265 } 1274 }
1266} 1275}
1267 1276
1277#if defined(CONFIG_DMA_NONCOHERENT)
1278
1279static int __cpuinitdata coherentio;
1280
1281static int __init setcoherentio(char *str)
1282{
1283 coherentio = 1;
1284
1285 return 1;
1286}
1287
1288__setup("coherentio", setcoherentio);
1289#endif
1290
1268void __cpuinit r4k_cache_init(void) 1291void __cpuinit r4k_cache_init(void)
1269{ 1292{
1270 extern void build_clear_page(void); 1293 extern void build_clear_page(void);
@@ -1324,14 +1347,22 @@ void __cpuinit r4k_cache_init(void)
1324 flush_data_cache_page = r4k_flush_data_cache_page; 1347 flush_data_cache_page = r4k_flush_data_cache_page;
1325 flush_icache_range = r4k_flush_icache_range; 1348 flush_icache_range = r4k_flush_icache_range;
1326 1349
1327#ifdef CONFIG_DMA_NONCOHERENT 1350#if defined(CONFIG_DMA_NONCOHERENT)
1328 _dma_cache_wback_inv = r4k_dma_cache_wback_inv; 1351 if (coherentio) {
1329 _dma_cache_wback = r4k_dma_cache_wback_inv; 1352 _dma_cache_wback_inv = (void *)cache_noop;
1330 _dma_cache_inv = r4k_dma_cache_inv; 1353 _dma_cache_wback = (void *)cache_noop;
1354 _dma_cache_inv = (void *)cache_noop;
1355 } else {
1356 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1357 _dma_cache_wback = r4k_dma_cache_wback_inv;
1358 _dma_cache_inv = r4k_dma_cache_inv;
1359 }
1331#endif 1360#endif
1332 1361
1333 build_clear_page(); 1362 build_clear_page();
1334 build_copy_page(); 1363 build_copy_page();
1364#if !defined(CONFIG_MIPS_CMP)
1335 local_r4k___flush_cache_all(NULL); 1365 local_r4k___flush_cache_all(NULL);
1366#endif
1336 coherency_setup(); 1367 coherency_setup();
1337} 1368}
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 235833af3a8b..05ac6c6123ca 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -221,7 +221,7 @@ void copy_user_highpage(struct page *to, struct page *from,
221 copy_page(vto, vfrom); 221 copy_page(vto, vfrom);
222 kunmap_atomic(vfrom, KM_USER0); 222 kunmap_atomic(vfrom, KM_USER0);
223 } 223 }
224 if (((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc) || 224 if ((!cpu_has_ic_fills_f_dc) ||
225 pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK)) 225 pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
226 flush_data_cache_page((unsigned long)vto); 226 flush_data_cache_page((unsigned long)vto);
227 kunmap_atomic(vto, KM_USER1); 227 kunmap_atomic(vto, KM_USER1);