diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-10-29 14:13:10 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-10-29 14:13:10 -0400 |
commit | b77d643ced576bdd1e918aebda869de74696cde9 (patch) | |
tree | bb5d708f4bbb48461923a28e63a8cf8bdd477dd7 /arch/mips/mm/uasm.c | |
parent | b4020c1b198c0f0c0b0ff0cfdd824a26b93edd6f (diff) | |
parent | 64575f918f3279d8487cf670dbefa956ce16a526 (diff) |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (46 commits)
ftrace/MIPS: Enable C Version of recordmcount
ftrace/MIPS: Add module support for C version of recordmcount
ftrace/MIPS: Add MIPS64 support for C version of recordmcount
MIPS: Make TASK_SIZE reflect proper size for both 32 and 64 bit processes.
MIPS: Allow UserLocal on MIPS_R1 processors
MIPS: Honor L2 bypass bit
MIPS: Add BMIPS CP0 register definitions
MIPS: Add BMIPS processor types to Kconfig
MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code
MIPS: Add support for hardware performance events (mipsxx)
MIPS: Perf-events: Add callchain support
MIPS: add support for hardware performance events (skeleton)
MIPS: add support for software performance events
MIPS: define local_xchg from xchg_local to atomic_long_xchg
MIPS: AR7: Add support for Titan (TNETV10xx) SoC variant
MIPS: AR7: Initialize GPIO earlier
MIPS: Add platform device and Kconfig for Octeon USB EHCI / OHCI
USB: Add EHCI and OHCH glue for OCTEON II SOCs.
MIPS: Octeon: Add register definitions for EHCI / OHCI USB glue logic.
MIPS: Octeon: Apply CN63XXP1 errata workarounds.
...
Diffstat (limited to 'arch/mips/mm/uasm.c')
-rw-r--r-- | arch/mips/mm/uasm.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index d2647a4e012b..23afdebc8e5c 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c | |||
@@ -405,7 +405,6 @@ I_u1u2u3(_mfc0) | |||
405 | I_u1u2u3(_mtc0) | 405 | I_u1u2u3(_mtc0) |
406 | I_u2u1u3(_ori) | 406 | I_u2u1u3(_ori) |
407 | I_u3u1u2(_or) | 407 | I_u3u1u2(_or) |
408 | I_u2s3u1(_pref) | ||
409 | I_0(_rfe) | 408 | I_0(_rfe) |
410 | I_u2s3u1(_sc) | 409 | I_u2s3u1(_sc) |
411 | I_u2s3u1(_scd) | 410 | I_u2s3u1(_scd) |
@@ -427,6 +426,25 @@ I_u1(_syscall); | |||
427 | I_u1u2s3(_bbit0); | 426 | I_u1u2s3(_bbit0); |
428 | I_u1u2s3(_bbit1); | 427 | I_u1u2s3(_bbit1); |
429 | 428 | ||
429 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
430 | #include <asm/octeon/octeon.h> | ||
431 | void __uasminit uasm_i_pref(u32 **buf, unsigned int a, signed int b, | ||
432 | unsigned int c) | ||
433 | { | ||
434 | if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5) | ||
435 | /* | ||
436 | * As per erratum Core-14449, replace prefetches 0-4, | ||
437 | * 6-24 with 'pref 28'. | ||
438 | */ | ||
439 | build_insn(buf, insn_pref, c, 28, b); | ||
440 | else | ||
441 | build_insn(buf, insn_pref, c, a, b); | ||
442 | } | ||
443 | UASM_EXPORT_SYMBOL(uasm_i_pref); | ||
444 | #else | ||
445 | I_u2s3u1(_pref) | ||
446 | #endif | ||
447 | |||
430 | /* Handle labels. */ | 448 | /* Handle labels. */ |
431 | void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) | 449 | void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) |
432 | { | 450 | { |