diff options
author | David Daney <ddaney@caviumnetworks.com> | 2010-12-21 17:19:10 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2011-01-18 13:30:22 -0500 |
commit | c42aef0947d717849f31965ecc0778707839bfe0 (patch) | |
tree | 7ce30dcb07e85b2af44045bb9be3e4da99074ae8 /arch/mips/mm/uasm.c | |
parent | e77c32fe284a4da1b4e0994890a4d3527812eb61 (diff) |
MIPS: Add DINSM to uasm.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1875/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/uasm.c')
-rw-r--r-- | arch/mips/mm/uasm.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 23afdebc8e5c..99f0347e82d2 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c | |||
@@ -68,7 +68,7 @@ enum opcode { | |||
68 | insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, | 68 | insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, |
69 | insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp, | 69 | insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp, |
70 | insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, | 70 | insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, |
71 | insn_dins, insn_syscall, insn_bbit0, insn_bbit1 | 71 | insn_dins, insn_dinsm, insn_syscall, insn_bbit0, insn_bbit1 |
72 | }; | 72 | }; |
73 | 73 | ||
74 | struct insn { | 74 | struct insn { |
@@ -142,6 +142,7 @@ static struct insn insn_table[] __uasminitdata = { | |||
142 | { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, | 142 | { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, |
143 | { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, | 143 | { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, |
144 | { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, | 144 | { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, |
145 | { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, | ||
145 | { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, | 146 | { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, |
146 | { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, | 147 | { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, |
147 | { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, | 148 | { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, |
@@ -340,6 +341,13 @@ Ip_u2u1msbu3(op) \ | |||
340 | } \ | 341 | } \ |
341 | UASM_EXPORT_SYMBOL(uasm_i##op); | 342 | UASM_EXPORT_SYMBOL(uasm_i##op); |
342 | 343 | ||
344 | #define I_u2u1msb32u3(op) \ | ||
345 | Ip_u2u1msbu3(op) \ | ||
346 | { \ | ||
347 | build_insn(buf, insn##op, b, a, c+d-33, c); \ | ||
348 | } \ | ||
349 | UASM_EXPORT_SYMBOL(uasm_i##op); | ||
350 | |||
343 | #define I_u1u2(op) \ | 351 | #define I_u1u2(op) \ |
344 | Ip_u1u2(op) \ | 352 | Ip_u1u2(op) \ |
345 | { \ | 353 | { \ |
@@ -422,6 +430,7 @@ I_0(_tlbwr) | |||
422 | I_u3u1u2(_xor) | 430 | I_u3u1u2(_xor) |
423 | I_u2u1u3(_xori) | 431 | I_u2u1u3(_xori) |
424 | I_u2u1msbu3(_dins); | 432 | I_u2u1msbu3(_dins); |
433 | I_u2u1msb32u3(_dinsm); | ||
425 | I_u1(_syscall); | 434 | I_u1(_syscall); |
426 | I_u1u2s3(_bbit0); | 435 | I_u1u2s3(_bbit0); |
427 | I_u1u2s3(_bbit1); | 436 | I_u1u2s3(_bbit1); |