diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:15 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:15 -0400 |
commit | 10cc3529072d5415fb040018a8a99aa7a60190b6 (patch) | |
tree | fe07fb5112c9c34c2aecfac982155307bc168f07 /arch/mips/mm/tlbex.c | |
parent | aeffdbbaff133b0c3989e20af5baa091d3d0b409 (diff) |
[MIPS] Allow hardwiring of the CPU type to a single type for optimization.
This saves a few k on systems which only ever ship with a single CPU type.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/tlbex.c')
-rw-r--r-- | arch/mips/mm/tlbex.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 73250741a0f9..c3da4fefbcb4 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c | |||
@@ -827,7 +827,7 @@ static __initdata u32 final_handler[64]; | |||
827 | */ | 827 | */ |
828 | static __init void __maybe_unused build_tlb_probe_entry(u32 **p) | 828 | static __init void __maybe_unused build_tlb_probe_entry(u32 **p) |
829 | { | 829 | { |
830 | switch (current_cpu_data.cputype) { | 830 | switch (current_cpu_type()) { |
831 | /* Found by experiment: R4600 v2.0 needs this, too. */ | 831 | /* Found by experiment: R4600 v2.0 needs this, too. */ |
832 | case CPU_R4600: | 832 | case CPU_R4600: |
833 | case CPU_R5000: | 833 | case CPU_R5000: |
@@ -860,7 +860,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, | |||
860 | case tlb_indexed: tlbw = i_tlbwi; break; | 860 | case tlb_indexed: tlbw = i_tlbwi; break; |
861 | } | 861 | } |
862 | 862 | ||
863 | switch (current_cpu_data.cputype) { | 863 | switch (current_cpu_type()) { |
864 | case CPU_R4000PC: | 864 | case CPU_R4000PC: |
865 | case CPU_R4000SC: | 865 | case CPU_R4000SC: |
866 | case CPU_R4000MC: | 866 | case CPU_R4000MC: |
@@ -1158,7 +1158,7 @@ static __init void build_adjust_context(u32 **p, unsigned int ctx) | |||
1158 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; | 1158 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
1159 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); | 1159 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
1160 | 1160 | ||
1161 | switch (current_cpu_data.cputype) { | 1161 | switch (current_cpu_type()) { |
1162 | case CPU_VR41XX: | 1162 | case CPU_VR41XX: |
1163 | case CPU_VR4111: | 1163 | case CPU_VR4111: |
1164 | case CPU_VR4121: | 1164 | case CPU_VR4121: |
@@ -1188,7 +1188,7 @@ static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) | |||
1188 | * in a different cacheline or a load instruction, probably any | 1188 | * in a different cacheline or a load instruction, probably any |
1189 | * memory reference, is between them. | 1189 | * memory reference, is between them. |
1190 | */ | 1190 | */ |
1191 | switch (current_cpu_data.cputype) { | 1191 | switch (current_cpu_type()) { |
1192 | case CPU_NEVADA: | 1192 | case CPU_NEVADA: |
1193 | i_LW(p, ptr, 0, ptr); | 1193 | i_LW(p, ptr, 0, ptr); |
1194 | GET_CONTEXT(p, tmp); /* get context reg */ | 1194 | GET_CONTEXT(p, tmp); /* get context reg */ |
@@ -1872,7 +1872,7 @@ void __init build_tlb_refill_handler(void) | |||
1872 | */ | 1872 | */ |
1873 | static int run_once = 0; | 1873 | static int run_once = 0; |
1874 | 1874 | ||
1875 | switch (current_cpu_data.cputype) { | 1875 | switch (current_cpu_type()) { |
1876 | case CPU_R2000: | 1876 | case CPU_R2000: |
1877 | case CPU_R3000: | 1877 | case CPU_R3000: |
1878 | case CPU_R3000A: | 1878 | case CPU_R3000A: |