MIPS: Fix TLBR-use hazards for R2 cores in the TLB reload handlers

MIPS R2 documents state that an execution hazard barrier is needed
after a TLBR before reading EntryLo.

Original patch by Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/5526/

1 files changed, 26 insertions, 0 deletions

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index afeef93f81a7..f0f4dc44f394 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1935,6 +1935,19 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
                 uasm_i_nop(&p);
 
                 uasm_i_tlbr(&p);
+
+                switch (current_cpu_type()) {
+                default:
+                        if (cpu_has_mips_r2) {
+                                uasm_i_ehb(&p);
+
+                case CPU_CAVIUM_OCTEON:
+                case CPU_CAVIUM_OCTEON_PLUS:
+                case CPU_CAVIUM_OCTEON2:
+                                break;
+                        }
+                }
+
                 /* Examine  entrylo 0 or 1 based on ptr. */
                 if (use_bbit_insns()) {
                         uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
@@ -1989,6 +2002,19 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
                 uasm_i_nop(&p);
 
                 uasm_i_tlbr(&p);
+
+                switch (current_cpu_type()) {
+                default:
+                        if (cpu_has_mips_r2) {
+                                uasm_i_ehb(&p);
+
+                case CPU_CAVIUM_OCTEON:
+                case CPU_CAVIUM_OCTEON_PLUS:
+                case CPU_CAVIUM_OCTEON2:
+                                break;
+                        }
+                }
+
                 /* Examine  entrylo 0 or 1 based on ptr. */
                 if (use_bbit_insns()) {
                         uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);