diff options
author | Fuxin Zhang <zhangfx@lemote.com> | 2007-06-06 02:52:43 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-07-10 12:33:02 -0400 |
commit | 2a21c7300b53b744d16903256a172d9cbcfdd03e (patch) | |
tree | 6a6f186fc7d4ab51fdda628a42f1fa845f189b8b /arch/mips/mm/tlb-r4k.c | |
parent | fee578fad1a29e6a149659e5467aedcae6897c06 (diff) |
[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2
Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/tlb-r4k.c')
-rw-r--r-- | arch/mips/mm/tlb-r4k.c | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 65160d4984d9..dcd6913dc1ff 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c | |||
@@ -48,6 +48,22 @@ extern void build_tlb_refill_handler(void); | |||
48 | 48 | ||
49 | #endif /* CONFIG_MIPS_MT_SMTC */ | 49 | #endif /* CONFIG_MIPS_MT_SMTC */ |
50 | 50 | ||
51 | #if defined(CONFIG_CPU_LOONGSON2) | ||
52 | /* | ||
53 | * LOONGSON2 has a 4 entry itlb which is a subset of dtlb, | ||
54 | * unfortrunately, itlb is not totally transparent to software. | ||
55 | */ | ||
56 | #define FLUSH_ITLB write_c0_diag(4); | ||
57 | |||
58 | #define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC) write_c0_diag(4); } | ||
59 | |||
60 | #else | ||
61 | |||
62 | #define FLUSH_ITLB | ||
63 | #define FLUSH_ITLB_VM(vma) | ||
64 | |||
65 | #endif | ||
66 | |||
51 | void local_flush_tlb_all(void) | 67 | void local_flush_tlb_all(void) |
52 | { | 68 | { |
53 | unsigned long flags; | 69 | unsigned long flags; |
@@ -73,6 +89,7 @@ void local_flush_tlb_all(void) | |||
73 | } | 89 | } |
74 | tlbw_use_hazard(); | 90 | tlbw_use_hazard(); |
75 | write_c0_entryhi(old_ctx); | 91 | write_c0_entryhi(old_ctx); |
92 | FLUSH_ITLB; | ||
76 | EXIT_CRITICAL(flags); | 93 | EXIT_CRITICAL(flags); |
77 | } | 94 | } |
78 | 95 | ||
@@ -136,6 +153,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, | |||
136 | } else { | 153 | } else { |
137 | drop_mmu_context(mm, cpu); | 154 | drop_mmu_context(mm, cpu); |
138 | } | 155 | } |
156 | FLUSH_ITLB; | ||
139 | EXIT_CRITICAL(flags); | 157 | EXIT_CRITICAL(flags); |
140 | } | 158 | } |
141 | } | 159 | } |
@@ -178,6 +196,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) | |||
178 | } else { | 196 | } else { |
179 | local_flush_tlb_all(); | 197 | local_flush_tlb_all(); |
180 | } | 198 | } |
199 | FLUSH_ITLB; | ||
181 | EXIT_CRITICAL(flags); | 200 | EXIT_CRITICAL(flags); |
182 | } | 201 | } |
183 | 202 | ||
@@ -210,6 +229,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |||
210 | 229 | ||
211 | finish: | 230 | finish: |
212 | write_c0_entryhi(oldpid); | 231 | write_c0_entryhi(oldpid); |
232 | FLUSH_ITLB_VM(vma); | ||
213 | EXIT_CRITICAL(flags); | 233 | EXIT_CRITICAL(flags); |
214 | } | 234 | } |
215 | } | 235 | } |
@@ -241,7 +261,7 @@ void local_flush_tlb_one(unsigned long page) | |||
241 | tlbw_use_hazard(); | 261 | tlbw_use_hazard(); |
242 | } | 262 | } |
243 | write_c0_entryhi(oldpid); | 263 | write_c0_entryhi(oldpid); |
244 | 264 | FLUSH_ITLB; | |
245 | EXIT_CRITICAL(flags); | 265 | EXIT_CRITICAL(flags); |
246 | } | 266 | } |
247 | 267 | ||
@@ -293,6 +313,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) | |||
293 | else | 313 | else |
294 | tlb_write_indexed(); | 314 | tlb_write_indexed(); |
295 | tlbw_use_hazard(); | 315 | tlbw_use_hazard(); |
316 | FLUSH_ITLB_VM(vma); | ||
296 | EXIT_CRITICAL(flags); | 317 | EXIT_CRITICAL(flags); |
297 | } | 318 | } |
298 | 319 | ||