diff options
author | Thiemo Seufer <ths@networkno.de> | 2005-02-25 08:11:18 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 14:30:44 -0400 |
commit | 685f779e6046e18b6190d2fbc9ef22e6b81c196e (patch) | |
tree | 978841c573762dd434ffee8288cf07d659e4d972 /arch/mips/mm/pg-sb1.c | |
parent | 65bda1a95d395c256818d1d8129487a4497b29d8 (diff) |
Fix initialization. Unbreak the wait-for-completion loops. Code cleanup.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/pg-sb1.c')
-rw-r--r-- | arch/mips/mm/pg-sb1.c | 46 |
1 files changed, 24 insertions, 22 deletions
diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c index 7a90ea383845..162bb155e695 100644 --- a/arch/mips/mm/pg-sb1.c +++ b/arch/mips/mm/pg-sb1.c | |||
@@ -207,30 +207,32 @@ typedef struct dmadscr_s { | |||
207 | u64 pad_b; | 207 | u64 pad_b; |
208 | } dmadscr_t; | 208 | } dmadscr_t; |
209 | 209 | ||
210 | static dmadscr_t page_descr[NR_CPUS] __attribute__((aligned(SMP_CACHE_BYTES))); | 210 | static dmadscr_t page_descr[DM_NUM_CHANNELS] __attribute__((aligned(SMP_CACHE_BYTES))); |
211 | 211 | ||
212 | void sb1_dma_init(void) | 212 | void sb1_dma_init(void) |
213 | { | 213 | { |
214 | int cpu = smp_processor_id(); | 214 | int i; |
215 | u64 base_val = CPHYSADDR(&page_descr[cpu]) | V_DM_DSCR_BASE_RINGSZ(1); | ||
216 | 215 | ||
217 | __raw_writeq(base_val, | 216 | for (i = 0; i < DM_NUM_CHANNELS; i++) { |
218 | IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); | 217 | u64 base_val = (u64)CPHYSADDR(&page_descr[i]) | V_DM_DSCR_BASE_RINGSZ(1); |
219 | __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, | 218 | void *base_reg = (void *)IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE)); |
220 | IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); | 219 | |
221 | __raw_writeq(base_val | M_DM_DSCR_BASE_ENABL, | 220 | __raw_writeq(base_val, base_reg); |
222 | IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); | 221 | __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg); |
222 | __raw_writeq(base_val | M_DM_DSCR_BASE_ENABL, base_reg); | ||
223 | } | ||
223 | } | 224 | } |
224 | 225 | ||
225 | void clear_page(void *page) | 226 | void clear_page(void *page) |
226 | { | 227 | { |
227 | int cpu = smp_processor_id(); | 228 | u64 to_phys = (u64)CPHYSADDR(page); |
229 | unsigned int cpu = smp_processor_id(); | ||
228 | 230 | ||
229 | /* if the page is above Kseg0, use old way */ | 231 | /* if the page is not in KSEG0, use old way */ |
230 | if ((long)KSEGX(page) != (long)CKSEG0) | 232 | if ((long)KSEGX(page) != (long)CKSEG0) |
231 | return clear_page_cpu(page); | 233 | return clear_page_cpu(page); |
232 | 234 | ||
233 | page_descr[cpu].dscr_a = CPHYSADDR(page) | M_DM_DSCRA_ZERO_MEM | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; | 235 | page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; |
234 | page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); | 236 | page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); |
235 | __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); | 237 | __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); |
236 | 238 | ||
@@ -239,32 +241,32 @@ void clear_page(void *page) | |||
239 | * reliable way to delay completion detection. | 241 | * reliable way to delay completion detection. |
240 | */ | 242 | */ |
241 | while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) | 243 | while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) |
242 | M_DM_DSCR_BASE_INTERRUPT))) | 244 | & M_DM_DSCR_BASE_INTERRUPT)) |
243 | ; | 245 | ; |
244 | __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); | 246 | __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); |
245 | } | 247 | } |
246 | 248 | ||
247 | void copy_page(void *to, void *from) | 249 | void copy_page(void *to, void *from) |
248 | { | 250 | { |
249 | unsigned long from_phys = CPHYSADDR(from); | 251 | u64 from_phys = (u64)CPHYSADDR(from); |
250 | unsigned long to_phys = CPHYSADDR(to); | 252 | u64 to_phys = (u64)CPHYSADDR(to); |
251 | int cpu = smp_processor_id(); | 253 | unsigned int cpu = smp_processor_id(); |
252 | 254 | ||
253 | /* if either page is above Kseg0, use old way */ | 255 | /* if any page is not in KSEG0, use old way */ |
254 | if ((long)KSEGX(to) != (long)CKSEG0 | 256 | if ((long)KSEGX(to) != (long)CKSEG0 |
255 | || (long)KSEGX(from) != (long)CKSEG0) | 257 | || (long)KSEGX(from) != (long)CKSEG0) |
256 | return copy_page_cpu(to, from); | 258 | return copy_page_cpu(to, from); |
257 | 259 | ||
258 | page_descr[cpu].dscr_a = CPHYSADDR(to_phys) | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; | 260 | page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; |
259 | page_descr[cpu].dscr_b = CPHYSADDR(from_phys) | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); | 261 | page_descr[cpu].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); |
260 | __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); | 262 | __raw_writeq(1, (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); |
261 | 263 | ||
262 | /* | 264 | /* |
263 | * Don't really want to do it this way, but there's no | 265 | * Don't really want to do it this way, but there's no |
264 | * reliable way to delay completion detection. | 266 | * reliable way to delay completion detection. |
265 | */ | 267 | */ |
266 | while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) & | 268 | while (!(__raw_readq((void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) |
267 | M_DM_DSCR_BASE_INTERRUPT))) | 269 | & M_DM_DSCR_BASE_INTERRUPT)) |
268 | ; | 270 | ; |
269 | __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); | 271 | __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); |
270 | } | 272 | } |