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authorSteve French <sfrench@us.ibm.com>2005-09-06 18:47:31 -0400
committerSteve French <sfrench@us.ibm.com>2005-09-06 18:47:31 -0400
commitc08319a9d50b5c9cb4fdb33728bd16497cf4ddd3 (patch)
tree5fbec9030029da1ec387c18b85f26f19ee50da44 /arch/mips/mm/pg-sb1.c
parentbfa0d75a1eee59f0577e3c1697ff570b77581a35 (diff)
parent4706df3d3c42af802597d82c8b1542c3d52eab23 (diff)
Merge with /pub/scm/linux/kernel/git/torvalds/linux-2.6.git
Diffstat (limited to 'arch/mips/mm/pg-sb1.c')
-rw-r--r--arch/mips/mm/pg-sb1.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c
index 59d131b5e536..1b6df7133c1e 100644
--- a/arch/mips/mm/pg-sb1.c
+++ b/arch/mips/mm/pg-sb1.c
@@ -114,7 +114,7 @@ static inline void copy_page_cpu(void *to, void *from)
114 " pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%1)\n" 114 " pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%1)\n"
115 " pref " SB1_PREF_LOAD_STREAMED_HINT ", -32(%0)\n" 115 " pref " SB1_PREF_LOAD_STREAMED_HINT ", -32(%0)\n"
116 "1: pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%1)\n" 116 "1: pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%1)\n"
117# ifdef CONFIG_MIPS64 117# ifdef CONFIG_64BIT
118 " ld $8, -128(%0) \n" /* Block copy a cacheline */ 118 " ld $8, -128(%0) \n" /* Block copy a cacheline */
119 " ld $9, -120(%0) \n" 119 " ld $9, -120(%0) \n"
120 " ld $10, -112(%0) \n" 120 " ld $10, -112(%0) \n"
@@ -148,7 +148,7 @@ static inline void copy_page_cpu(void *to, void *from)
148 " daddiu %0, %0, -128 \n" 148 " daddiu %0, %0, -128 \n"
149 " daddiu %1, %1, -128 \n" 149 " daddiu %1, %1, -128 \n"
150#endif 150#endif
151#ifdef CONFIG_MIPS64 151#ifdef CONFIG_64BIT
152 " ld $8, 0(%0) \n" /* Block copy a cacheline */ 152 " ld $8, 0(%0) \n" /* Block copy a cacheline */
153 "1: ld $9, 8(%0) \n" 153 "1: ld $9, 8(%0) \n"
154 " ld $10, 16(%0) \n" 154 " ld $10, 16(%0) \n"
@@ -178,7 +178,7 @@ static inline void copy_page_cpu(void *to, void *from)
178 " daddiu %0, %0, 32 \n" 178 " daddiu %0, %0, 32 \n"
179 " daddiu %1, %1, 32 \n" 179 " daddiu %1, %1, 32 \n"
180 " bnel %0, %2, 1b \n" 180 " bnel %0, %2, 1b \n"
181#ifdef CONFIG_MIPS64 181#ifdef CONFIG_64BIT
182 " ld $8, 0(%0) \n" 182 " ld $8, 0(%0) \n"
183#else 183#else
184 " lw $2, 0(%0) \n" 184 " lw $2, 0(%0) \n"
@@ -186,7 +186,7 @@ static inline void copy_page_cpu(void *to, void *from)
186 " .set pop \n" 186 " .set pop \n"
187 : "+r" (src), "+r" (dst) 187 : "+r" (src), "+r" (dst)
188 : "r" (end) 188 : "r" (end)
189#ifdef CONFIG_MIPS64 189#ifdef CONFIG_64BIT
190 : "$8","$9","$10","$11","memory"); 190 : "$8","$9","$10","$11","memory");
191#else 191#else
192 : "$2","$3","$6","$7","$8","$9","$10","$11","memory"); 192 : "$2","$3","$6","$7","$8","$9","$10","$11","memory");
@@ -198,7 +198,7 @@ static inline void copy_page_cpu(void *to, void *from)
198 198
199/* 199/*
200 * Pad descriptors to cacheline, since each is exclusively owned by a 200 * Pad descriptors to cacheline, since each is exclusively owned by a
201 * particular CPU. 201 * particular CPU.
202 */ 202 */
203typedef struct dmadscr_s { 203typedef struct dmadscr_s {
204 u64 dscr_a; 204 u64 dscr_a;