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authorRalf Baechle <ralf@linux-mips.org>2013-01-22 06:59:30 -0500
committerRalf Baechle <ralf@linux-mips.org>2013-02-01 04:00:22 -0500
commit7034228792cc561e79ff8600f02884bd4c80e287 (patch)
tree89b77af37d087d9de236fc5d21f60bf552d0a2c6 /arch/mips/mm/cex-oct.S
parent405ab01c70e18058d9c01a1256769a61fc65413e (diff)
MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/cex-oct.S')
-rw-r--r--arch/mips/mm/cex-oct.S36
1 files changed, 18 insertions, 18 deletions
diff --git a/arch/mips/mm/cex-oct.S b/arch/mips/mm/cex-oct.S
index 3db8553fcd34..9029092aa740 100644
--- a/arch/mips/mm/cex-oct.S
+++ b/arch/mips/mm/cex-oct.S
@@ -18,7 +18,7 @@
18 */ 18 */
19 LEAF(except_vec2_octeon) 19 LEAF(except_vec2_octeon)
20 20
21 .set push 21 .set push
22 .set mips64r2 22 .set mips64r2
23 .set noreorder 23 .set noreorder
24 .set noat 24 .set noat
@@ -27,19 +27,19 @@
27 /* due to an errata we need to read the COP0 CacheErr (Dcache) 27 /* due to an errata we need to read the COP0 CacheErr (Dcache)
28 * before any cache/DRAM access */ 28 * before any cache/DRAM access */
29 29
30 rdhwr k0, $0 /* get core_id */ 30 rdhwr k0, $0 /* get core_id */
31 PTR_LA k1, cache_err_dcache 31 PTR_LA k1, cache_err_dcache
32 sll k0, k0, 3 32 sll k0, k0, 3
33 PTR_ADDU k1, k0, k1 /* k1 = &cache_err_dcache[core_id] */ 33 PTR_ADDU k1, k0, k1 /* k1 = &cache_err_dcache[core_id] */
34 34
35 dmfc0 k0, CP0_CACHEERR, 1 35 dmfc0 k0, CP0_CACHEERR, 1
36 sd k0, (k1) 36 sd k0, (k1)
37 dmtc0 $0, CP0_CACHEERR, 1 37 dmtc0 $0, CP0_CACHEERR, 1
38 38
39 /* check whether this is a nested exception */ 39 /* check whether this is a nested exception */
40 mfc0 k1, CP0_STATUS 40 mfc0 k1, CP0_STATUS
41 andi k1, k1, ST0_EXL 41 andi k1, k1, ST0_EXL
42 beqz k1, 1f 42 beqz k1, 1f
43 nop 43 nop
44 j cache_parity_error_octeon_non_recoverable 44 j cache_parity_error_octeon_non_recoverable
45 nop 45 nop
@@ -48,22 +48,22 @@
481: j handle_cache_err 481: j handle_cache_err
49 nop 49 nop
50 50
51 .set pop 51 .set pop
52 END(except_vec2_octeon) 52 END(except_vec2_octeon)
53 53
54 /* We need to jump to handle_cache_err so that the previous handler 54 /* We need to jump to handle_cache_err so that the previous handler
55 * can fit within 0x80 bytes. We also move from 0xFFFFFFFFAXXXXXXX 55 * can fit within 0x80 bytes. We also move from 0xFFFFFFFFAXXXXXXX
56 * space (uncached) to the 0xFFFFFFFF8XXXXXXX space (cached). */ 56 * space (uncached) to the 0xFFFFFFFF8XXXXXXX space (cached). */
57 LEAF(handle_cache_err) 57 LEAF(handle_cache_err)
58 .set push 58 .set push
59 .set noreorder 59 .set noreorder
60 .set noat 60 .set noat
61 61
62 SAVE_ALL 62 SAVE_ALL
63 KMODE 63 KMODE
64 jal cache_parity_error_octeon_recoverable 64 jal cache_parity_error_octeon_recoverable
65 nop 65 nop
66 j ret_from_exception 66 j ret_from_exception
67 nop 67 nop
68 68
69 .set pop 69 .set pop