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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2006-09-01 11:43:07 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-10-01 18:16:58 -0400
commitc59a0f15be6e586aa0fe1fb5c7f740005c36ec56 (patch)
tree868306f72db9b8113345b2d1eb810323805ca0c3 /arch/mips/mm/c-tx39.c
parent1a6183f2e6f0fa2d1898f0228559df15a89a1ffe (diff)
[MIPS] Remove __flush_icache_page
__flash_icache_page is unused, so kill it. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/c-tx39.c')
-rw-r--r--arch/mips/mm/c-tx39.c29
1 files changed, 0 insertions, 29 deletions
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 932a09d7ef84..f32ebde30ccf 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -248,33 +248,6 @@ static void tx39_flush_icache_range(unsigned long start, unsigned long end)
248 } 248 }
249} 249}
250 250
251/*
252 * Ok, this seriously sucks. We use them to flush a user page but don't
253 * know the virtual address, so we have to blast away the whole icache
254 * which is significantly more expensive than the real thing. Otoh we at
255 * least know the kernel address of the page so we can flush it
256 * selectivly.
257 */
258static void tx39_flush_icache_page(struct vm_area_struct *vma, struct page *page)
259{
260 unsigned long addr;
261 /*
262 * If there's no context yet, or the page isn't executable, no icache
263 * flush is needed.
264 */
265 if (!(vma->vm_flags & VM_EXEC))
266 return;
267
268 addr = (unsigned long) page_address(page);
269 tx39_blast_dcache_page(addr);
270
271 /*
272 * We're not sure of the virtual address(es) involved here, so
273 * we have to flush the entire I-cache.
274 */
275 tx39_blast_icache();
276}
277
278static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size) 251static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
279{ 252{
280 unsigned long end; 253 unsigned long end;
@@ -382,7 +355,6 @@ void __init tx39_cache_init(void)
382 flush_cache_mm = (void *) tx39h_flush_icache_all; 355 flush_cache_mm = (void *) tx39h_flush_icache_all;
383 flush_cache_range = (void *) tx39h_flush_icache_all; 356 flush_cache_range = (void *) tx39h_flush_icache_all;
384 flush_cache_page = (void *) tx39h_flush_icache_all; 357 flush_cache_page = (void *) tx39h_flush_icache_all;
385 __flush_icache_page = (void *) tx39h_flush_icache_all;
386 flush_icache_range = (void *) tx39h_flush_icache_all; 358 flush_icache_range = (void *) tx39h_flush_icache_all;
387 359
388 flush_cache_sigtramp = (void *) tx39h_flush_icache_all; 360 flush_cache_sigtramp = (void *) tx39h_flush_icache_all;
@@ -408,7 +380,6 @@ void __init tx39_cache_init(void)
408 flush_cache_mm = tx39_flush_cache_mm; 380 flush_cache_mm = tx39_flush_cache_mm;
409 flush_cache_range = tx39_flush_cache_range; 381 flush_cache_range = tx39_flush_cache_range;
410 flush_cache_page = tx39_flush_cache_page; 382 flush_cache_page = tx39_flush_cache_page;
411 __flush_icache_page = tx39_flush_icache_page;
412 flush_icache_range = tx39_flush_icache_range; 383 flush_icache_range = tx39_flush_icache_range;
413 384
414 flush_cache_sigtramp = tx39_flush_cache_sigtramp; 385 flush_cache_sigtramp = tx39_flush_cache_sigtramp;