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authorRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:05 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:05 -0400
commit641e97f318870921d048154af6807e46e43c307a (patch)
tree6e0984a1bc8932db848be3fdb104a92c97fe341a /arch/mips/mm/c-r4k.c
parent424b28ba4d25fc41abdb7e6fa90e132f0d9558fb (diff)
[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
-rw-r--r--arch/mips/mm/c-r4k.c22
1 files changed, 18 insertions, 4 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index bad571971bf6..738b89803a44 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -9,6 +9,7 @@
9 */ 9 */
10#include <linux/init.h> 10#include <linux/init.h>
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/linkage.h>
12#include <linux/sched.h> 13#include <linux/sched.h>
13#include <linux/mm.h> 14#include <linux/mm.h>
14#include <linux/bitops.h> 15#include <linux/bitops.h>
@@ -948,12 +949,16 @@ static void __init probe_pcache(void)
948 switch (c->cputype) { 949 switch (c->cputype) {
949 case CPU_20KC: 950 case CPU_20KC:
950 case CPU_25KF: 951 case CPU_25KF:
952 case CPU_SB1:
953 case CPU_SB1A:
951 c->dcache.flags |= MIPS_CACHE_PINDEX; 954 c->dcache.flags |= MIPS_CACHE_PINDEX;
955 break;
956
952 case CPU_R10000: 957 case CPU_R10000:
953 case CPU_R12000: 958 case CPU_R12000:
954 case CPU_R14000: 959 case CPU_R14000:
955 case CPU_SB1:
956 break; 960 break;
961
957 case CPU_24K: 962 case CPU_24K:
958 case CPU_34K: 963 case CPU_34K:
959 case CPU_74K: 964 case CPU_74K:
@@ -1235,11 +1240,20 @@ void __init r4k_cache_init(void)
1235{ 1240{
1236 extern void build_clear_page(void); 1241 extern void build_clear_page(void);
1237 extern void build_copy_page(void); 1242 extern void build_copy_page(void);
1238 extern char except_vec2_generic; 1243 extern char __weak except_vec2_generic;
1244 extern char __weak except_vec2_sb1;
1239 struct cpuinfo_mips *c = &current_cpu_data; 1245 struct cpuinfo_mips *c = &current_cpu_data;
1240 1246
1241 /* Default cache error handler for R4000 and R5000 family */ 1247 switch (c->cputype) {
1242 set_uncached_handler (0x100, &except_vec2_generic, 0x80); 1248 case CPU_SB1:
1249 case CPU_SB1A:
1250 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1251 break;
1252
1253 default:
1254 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1255 break;
1256 }
1243 1257
1244 probe_pcache(); 1258 probe_pcache();
1245 setup_scache(); 1259 setup_scache();