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authorManuel Lauss <mano@roarinelk.homelinux.net>2009-03-25 12:49:28 -0400
committerRalf Baechle <ralf@linux-mips.org>2009-03-30 08:49:45 -0400
commit270717a8a0e5f03c104a6d47466036b615edfcde (patch)
tree33b319a455d24b246df5200e523aa66a7341cb42 /arch/mips/mm/c-r4k.c
parent76544504aebc606b8279a5314595af5d568e7fea (diff)
MIPS: Alchemy: unify CPU model constants.
This patch removes the various CPU_AU1??? model constants in favor of a single CPU_ALCHEMY one. All currently existing Alchemy models are identical in terms of cpu core and cache size/organization. The parts of the mips kernel which need to know the exact CPU revision extract it from the c0_prid register already; and finally nothing else in-tree depends on those any more. Should a new variant with slightly different "company options" and/or "processor revision" bits in c0_prid appear, it will be supported immediately (minus an exact model string in cpuinfo). Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
-rw-r--r--arch/mips/mm/c-r4k.c17
1 files changed, 5 insertions, 12 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 871e828bc62a..58d9075e86fe 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1026,13 +1026,7 @@ static void __cpuinit probe_pcache(void)
1026 c->icache.flags |= MIPS_CACHE_VTAG; 1026 c->icache.flags |= MIPS_CACHE_VTAG;
1027 break; 1027 break;
1028 1028
1029 case CPU_AU1000: 1029 case CPU_ALCHEMY:
1030 case CPU_AU1500:
1031 case CPU_AU1100:
1032 case CPU_AU1550:
1033 case CPU_AU1200:
1034 case CPU_AU1210:
1035 case CPU_AU1250:
1036 c->icache.flags |= MIPS_CACHE_IC_F_DC; 1030 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1037 break; 1031 break;
1038 } 1032 }
@@ -1244,7 +1238,7 @@ void au1x00_fixup_config_od(void)
1244 /* 1238 /*
1245 * Au1100 errata actually keeps silence about this bit, so we set it 1239 * Au1100 errata actually keeps silence about this bit, so we set it
1246 * just in case for those revisions that require it to be set according 1240 * just in case for those revisions that require it to be set according
1247 * to arch/mips/au1000/common/cputable.c 1241 * to the (now gone) cpu table.
1248 */ 1242 */
1249 case 0x02030200: /* Au1100 AB */ 1243 case 0x02030200: /* Au1100 AB */
1250 case 0x02030201: /* Au1100 BA */ 1244 case 0x02030201: /* Au1100 BA */
@@ -1314,11 +1308,10 @@ static void __cpuinit coherency_setup(void)
1314 break; 1308 break;
1315 /* 1309 /*
1316 * We need to catch the early Alchemy SOCs with 1310 * We need to catch the early Alchemy SOCs with
1317 * the write-only co_config.od bit and set it back to one... 1311 * the write-only co_config.od bit and set it back to one on:
1312 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
1318 */ 1313 */
1319 case CPU_AU1000: /* rev. DA, HA, HB */ 1314 case CPU_ALCHEMY:
1320 case CPU_AU1100: /* rev. AB, BA, BC ?? */
1321 case CPU_AU1500: /* rev. AB */
1322 au1x00_fixup_config_od(); 1315 au1x00_fixup_config_od();
1323 break; 1316 break;
1324 1317