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authorRalf Baechle <ralf@linux-mips.org>2005-02-06 16:55:49 -0500
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:30:26 -0400
commitae6aafe30917c4c9f3533471d491b5e7c2fbe61a (patch)
treeae1a7c88853a2f9d982db41f80f7235ce37b4f50 /arch/mips/mm/c-r4k.c
parent0efe27617e67448dfe78e7cebde3a6f9eadf1223 (diff)
Move missplaced code line to the right place.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
-rw-r--r--arch/mips/mm/c-r4k.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 1466c497beab..726e899486a3 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1012,15 +1012,14 @@ static void __init probe_pcache(void)
1012 * with that for us so we don't need to take care ourselves. 1012 * with that for us so we don't need to take care ourselves.
1013 */ 1013 */
1014 switch (c->cputype) { 1014 switch (c->cputype) {
1015 if (c->dcache.waysize > PAGE_SIZE)
1016
1017 case CPU_R10000: 1015 case CPU_R10000:
1018 case CPU_R12000: 1016 case CPU_R12000:
1019 break; 1017 break;
1020 case CPU_24K: 1018 case CPU_24K:
1021 if (!(read_c0_config7() & (1 << 16))) 1019 if (!(read_c0_config7() & (1 << 16)))
1022 default: 1020 default:
1023 c->dcache.flags |= MIPS_CACHE_ALIASES; 1021 if (c->dcache.waysize > PAGE_SIZE)
1022 c->dcache.flags |= MIPS_CACHE_ALIASES;
1024 } 1023 }
1025 1024
1026 switch (c->cputype) { 1025 switch (c->cputype) {