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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2006-02-09 10:39:06 -0500
committerRalf Baechle <ralf@linux-mips.org>2006-02-14 14:13:24 -0500
commit41700e73995d6c814932cb55e12525bd34be1ca5 (patch)
tree559759cbda13bb50720cfd0e317fa65a467d59fa /arch/mips/mm/c-r4k.c
parent63077519899721120b61d663a68adced068a459d (diff)
[MIPS] Add protected_blast_icache_range, blast_icache_range, etc.
Add blast_xxx_range(), protected_blast_xxx_range() etc. for common use. They are built by __BUILD_BLAST_CACHE_RANGE(). Use protected_cache_op() macro for various protected_ routines. Output code should be logically same. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
-rw-r--r--arch/mips/mm/c-r4k.c104
1 files changed, 14 insertions, 90 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index e51c38cef88e..1b71d91e8268 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -471,61 +471,29 @@ struct flush_icache_range_args {
471static inline void local_r4k_flush_icache_range(void *args) 471static inline void local_r4k_flush_icache_range(void *args)
472{ 472{
473 struct flush_icache_range_args *fir_args = args; 473 struct flush_icache_range_args *fir_args = args;
474 unsigned long dc_lsize = cpu_dcache_line_size();
475 unsigned long ic_lsize = cpu_icache_line_size();
476 unsigned long sc_lsize = cpu_scache_line_size();
477 unsigned long start = fir_args->start; 474 unsigned long start = fir_args->start;
478 unsigned long end = fir_args->end; 475 unsigned long end = fir_args->end;
479 unsigned long addr, aend;
480 476
481 if (!cpu_has_ic_fills_f_dc) { 477 if (!cpu_has_ic_fills_f_dc) {
482 if (end - start > dcache_size) { 478 if (end - start > dcache_size) {
483 r4k_blast_dcache(); 479 r4k_blast_dcache();
484 } else { 480 } else {
485 R4600_HIT_CACHEOP_WAR_IMPL; 481 R4600_HIT_CACHEOP_WAR_IMPL;
486 addr = start & ~(dc_lsize - 1); 482 protected_blast_dcache_range(start, end);
487 aend = (end - 1) & ~(dc_lsize - 1);
488
489 while (1) {
490 /* Hit_Writeback_Inv_D */
491 protected_writeback_dcache_line(addr);
492 if (addr == aend)
493 break;
494 addr += dc_lsize;
495 }
496 } 483 }
497 484
498 if (!cpu_icache_snoops_remote_store) { 485 if (!cpu_icache_snoops_remote_store) {
499 if (end - start > scache_size) { 486 if (end - start > scache_size)
500 r4k_blast_scache(); 487 r4k_blast_scache();
501 } else { 488 else
502 addr = start & ~(sc_lsize - 1); 489 protected_blast_scache_range(start, end);
503 aend = (end - 1) & ~(sc_lsize - 1);
504
505 while (1) {
506 /* Hit_Writeback_Inv_SD */
507 protected_writeback_scache_line(addr);
508 if (addr == aend)
509 break;
510 addr += sc_lsize;
511 }
512 }
513 } 490 }
514 } 491 }
515 492
516 if (end - start > icache_size) 493 if (end - start > icache_size)
517 r4k_blast_icache(); 494 r4k_blast_icache();
518 else { 495 else
519 addr = start & ~(ic_lsize - 1); 496 protected_blast_icache_range(start, end);
520 aend = (end - 1) & ~(ic_lsize - 1);
521 while (1) {
522 /* Hit_Invalidate_I */
523 protected_flush_icache_line(addr);
524 if (addr == aend)
525 break;
526 addr += ic_lsize;
527 }
528 }
529} 497}
530 498
531static void r4k_flush_icache_range(unsigned long start, unsigned long end) 499static void r4k_flush_icache_range(unsigned long start, unsigned long end)
@@ -619,27 +587,14 @@ static void r4k_flush_icache_page(struct vm_area_struct *vma,
619 587
620static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) 588static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
621{ 589{
622 unsigned long end, a;
623
624 /* Catch bad driver code */ 590 /* Catch bad driver code */
625 BUG_ON(size == 0); 591 BUG_ON(size == 0);
626 592
627 if (cpu_has_subset_pcaches) { 593 if (cpu_has_subset_pcaches) {
628 unsigned long sc_lsize = cpu_scache_line_size(); 594 if (size >= scache_size)
629
630 if (size >= scache_size) {
631 r4k_blast_scache(); 595 r4k_blast_scache();
632 return; 596 else
633 } 597 blast_scache_range(addr, addr + size);
634
635 a = addr & ~(sc_lsize - 1);
636 end = (addr + size - 1) & ~(sc_lsize - 1);
637 while (1) {
638 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
639 if (a == end)
640 break;
641 a += sc_lsize;
642 }
643 return; 598 return;
644 } 599 }
645 600
@@ -651,17 +606,8 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
651 if (size >= dcache_size) { 606 if (size >= dcache_size) {
652 r4k_blast_dcache(); 607 r4k_blast_dcache();
653 } else { 608 } else {
654 unsigned long dc_lsize = cpu_dcache_line_size();
655
656 R4600_HIT_CACHEOP_WAR_IMPL; 609 R4600_HIT_CACHEOP_WAR_IMPL;
657 a = addr & ~(dc_lsize - 1); 610 blast_dcache_range(addr, addr + size);
658 end = (addr + size - 1) & ~(dc_lsize - 1);
659 while (1) {
660 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
661 if (a == end)
662 break;
663 a += dc_lsize;
664 }
665 } 611 }
666 612
667 bc_wback_inv(addr, size); 613 bc_wback_inv(addr, size);
@@ -669,44 +615,22 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
669 615
670static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) 616static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
671{ 617{
672 unsigned long end, a;
673
674 /* Catch bad driver code */ 618 /* Catch bad driver code */
675 BUG_ON(size == 0); 619 BUG_ON(size == 0);
676 620
677 if (cpu_has_subset_pcaches) { 621 if (cpu_has_subset_pcaches) {
678 unsigned long sc_lsize = cpu_scache_line_size(); 622 if (size >= scache_size)
679
680 if (size >= scache_size) {
681 r4k_blast_scache(); 623 r4k_blast_scache();
682 return; 624 else
683 } 625 blast_scache_range(addr, addr + size);
684
685 a = addr & ~(sc_lsize - 1);
686 end = (addr + size - 1) & ~(sc_lsize - 1);
687 while (1) {
688 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
689 if (a == end)
690 break;
691 a += sc_lsize;
692 }
693 return; 626 return;
694 } 627 }
695 628
696 if (size >= dcache_size) { 629 if (size >= dcache_size) {
697 r4k_blast_dcache(); 630 r4k_blast_dcache();
698 } else { 631 } else {
699 unsigned long dc_lsize = cpu_dcache_line_size();
700
701 R4600_HIT_CACHEOP_WAR_IMPL; 632 R4600_HIT_CACHEOP_WAR_IMPL;
702 a = addr & ~(dc_lsize - 1); 633 blast_dcache_range(addr, addr + size);
703 end = (addr + size - 1) & ~(dc_lsize - 1);
704 while (1) {
705 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
706 if (a == end)
707 break;
708 a += dc_lsize;
709 }
710 } 634 }
711 635
712 bc_inv(addr, size); 636 bc_inv(addr, size);