[PATCH] mips: nuke trailing whitespace

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 8 insertions, 8 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 20d40725e5bb..5ea84bc98c6a 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -126,13 +126,13 @@ static inline void tx49_blast_icache32(void)
 
         CACHE32_UNROLL32_ALIGN2;
         /* I'm in even chunk.  blast odd chunks */
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
                         cache32_unroll32(addr|ws,Index_Invalidate_I);
         CACHE32_UNROLL32_ALIGN;
         /* I'm in odd chunk.  blast even chunks */
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x400 * 2) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x400 * 2)
                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -156,13 +156,13 @@ static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 
         CACHE32_UNROLL32_ALIGN2;
         /* I'm in even chunk.  blast odd chunks */
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
                         cache32_unroll32(addr|ws,Index_Invalidate_I);
         CACHE32_UNROLL32_ALIGN;
         /* I'm in odd chunk.  blast even chunks */
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x400 * 2) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x400 * 2)
                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 }