Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (141 commits)
  MIPS: Alchemy: defconfig updates
  MIPS: Alchemy: Fix Au1100 ethernet build failure
  MIPS: Alchemy: Repair db1500/bosporus builds
  MIPS: ARC: Cleanup unused definitions from sgialib.h
  MIPS: Cobalt: convert legacy port addresses to GT-64111 bus addresses
  MIPS: Alchemy: use 36bit addresses for PCMCIA resources.
  MIPS: Cobalt: Fix theoretical port aliasing issue
  MIPS: Use ALIGN(x, bytes) instead of __ALIGN_MASK(x, bytes - 1)
  MIPS: Crazy spinlock speed test.
  MIPS: Optimize spinlocks.
  MIPS: Alchemy: devboard PM needs to save CPLD registers.
  MIPS: PowerTV: Eliminate duplicate opcode definition macros
  MIPS: Lemote 2F: Move printks out of port_access_lock.
  MIPS: PNX833x: Convert IRQ controller locks to raw spinlocks.
  MIPS: Octeon: Replace spinlock with raw_spinlocks in dma-octeon.c.
  MIPS: Octeon: Replace rwlocks in irq_chip handlers with raw_spinlocks.
  MIPS: Octeon: Convert octeon_irq_msi_lock to raw spinlock.
  MIPS: Loongson: Remove pointless sample_lock from oprofile code.
  MIPS: SNI: Convert sni_rm200_i8259A_lock to raw spinlock.
  MIPS: i8259: Convert IRQ controller lock to raw spinlock.
  ...

1 files changed, 4 insertions, 4 deletions

diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index e06f1af760a7..0f9c488044d1 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -183,6 +183,7 @@ static void __cpuinit probe_octeon(void)
 
         switch (c->cputype) {
         case CPU_CAVIUM_OCTEON:
+        case CPU_CAVIUM_OCTEON_PLUS:
                 config1 = read_c0_config1();
                 c->icache.linesz = 2 << ((config1 >> 19) & 7);
                 c->icache.sets = 64 << ((config1 >> 22) & 7);
@@ -192,10 +193,10 @@ static void __cpuinit probe_octeon(void)
                         c->icache.sets * c->icache.ways * c->icache.linesz;
                 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
                 c->dcache.linesz = 128;
-                if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
-                        c->dcache.sets = 1; /* CN3XXX has one Dcache set */
-                else
+                if (c->cputype == CPU_CAVIUM_OCTEON_PLUS)
                         c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
+                else
+                        c->dcache.sets = 1; /* CN3XXX has one Dcache set */
                 c->dcache.ways = 64;
                 dcache_size =
                         c->dcache.sets * c->dcache.ways * c->dcache.linesz;
@@ -305,4 +306,3 @@ asmlinkage void cache_parity_error_octeon_non_recoverable(void)
 {
         cache_parity_error_octeon(1);
 }
-